Memory Refresh Command Merging for Bus-Efficient Mode Register Reads

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Solution Overview

Problem

The frequent polling of operating parameters in memory devices, such as device temperature, to adjust refresh rates consumes significant bandwidth on the command/address bus, leading to congestion and inefficiency.

Innovation Solution

A memory device configured to perform both a refresh operation and a mode register read in response to a single refresh command, reducing the need for dedicated mode register read commands and minimizing command/address bus bandwidth consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If frequent polling of operating parameters is performed to adjust refresh rates, then reliability of memory operation is improved, but command/address bus bandwidth consumption increases

Engineering Contradiction:
Improvememory operation reliabilityVSAvoidcommand/address bus bandwidth
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines a mode register read operation with a refresh command, allowing both operations to be performed in response to a single command signal. This merging eliminates the need for separate polling commands, reducing command/address bus bandwidth consumption while maintaining the ability to monitor operating parameters for reliable memory operation

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The refresh command is designed to serve multiple functions: it performs the mandatory refresh operation on memory cells and simultaneously enables mode register read operations for polling operating parameters. This multi-functionality reduces the number of dedicated polling commands needed, thereby conserving bus bandwidth

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If dedicated mode register read commands are issued for polling, then measurement precision of operating parameters is improved, but device complexity increases

Engineering Contradiction:
Improveoperating parameter measurementVSAvoidcommand processing complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The refresh command structure is enhanced to universally support both refresh operations and mode register read operations. By embedding mode register read capability within the existing refresh command framework, the patent avoids adding complex dedicated polling command structures while maintaining precise operating parameter measurement

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If multiple separate commands are used for refresh and mode register read, then ease of operation is improved, but productivity decreases

Engineering Contradiction:
Improvecommand issuance simplicityVSAvoidmemory operation throughput
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

By merging the mode register read operation into the refresh command response, the patent enables polling of operating parameters without requiring additional command cycles. This combination maintains operational simplicity while improving productivity by eliminating command overhead and reducing bus congestion

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12475067B2Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
Publication Date: 2025.11.18 LODESTAR LICENSING GROUP LLC
  • US12475067B2 patent drawing
  • US12475067B2 patent drawing
  • US12475067B2 patent drawing

AI summary

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.