Memory Refresh Control Circuit for Row Hammer Attack Mitigation
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Solution Overview
Problem
Volatile memory systems face increased data decay rates due to certain access patterns, both inadvertent and malicious, which can lead to data manipulation and loss, necessitating a method to detect and mitigate such patterns.
Innovation Solution
A memory system with a refresh control circuit that monitors access patterns, detects attacks, and sends alert signals to the controller to suspend operations, allowing the memory to perform refresh operations and slow down attack rates by specifying a pause duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory operates with high-speed access patterns, then productivity is improved, but data decay rate increases and reliability deteriorates
Solution Approach 1:
The refresh control circuit performs preliminary detection of access patterns to identify potential row hammer attacks before they cause significant data decay. By monitoring access patterns in advance and proactively pausing operations when threats are detected, the system prevents data integrity issues rather than reacting after damage occurs.
Solution Approach 2:
The system implements continuous feedback by monitoring access patterns, detecting anomalies, and dynamically adjusting operations by pausing or refreshing memory rows. The refresh control circuit receives feedback from access pattern analysis and responds by controlling refresh operations to maintain data integrity while allowing normal operations to resume after threats are mitigated.
2Reliability
If the memory performs frequent refresh operations to prevent data decay, then reliability is improved, but productivity decreases due to operation interruptions
Solution Approach 1:
Instead of performing global refresh operations across the entire memory, the refresh control circuit applies refresh operations locally to specific rows that are identified as victims of row hammer attacks. This targeted approach maintains data integrity for affected rows while minimizing interruptions to overall memory operations and productivity.
Solution Approach 2:
The system performs refresh operations selectively on only the necessary portions of memory that are under attack, rather than refreshing the entire memory array. This partial action approach provides sufficient protection against data decay while minimizing the impact on overall system productivity.
3Reliability
If the system monitors access patterns continuously to detect attacks, then reliability is improved, but device complexity increases
Solution Approach 1:
The refresh control circuit performs multiple functions: it controls refresh operations, monitors access patterns, detects row hammer attacks, and manages pausing of memory operations. By consolidating these diverse functions into a single control circuit, the system achieves comprehensive attack detection and protection without proportionally increasing device complexity.
Data Source
AI summary
Apparatuses, systems, and methods for a memory-directed access pause. A controller may perform access operations on a memory by providing commands and addresses. The memory may monitor the addresses to determine if one or more forms of attack (deliberate or inadvertent) is occurring. If an attack is detected, the memory may issue an alert signal (e.g., along an alert bus) and also provide pause data (e.g., along a data bus). The pause data may specify a length of time, and responsive to the alert and the pause data, the controller may suspend access operations on the memory for the length of time specified in the pause data. The memory may use the time when access operations are paused to refresh itself, for example to heal the damage caused by the attack).