Semiconductor Memory Refresh Control via Segmented Block Timing
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Solution Overview
Problem
As memory capacity increases in semiconductor devices, the limited refresh time (tRFC) becomes insufficient, leading to potential data loss due to word line disturbance, where data in memory cells adjacent to frequently activated word lines can be corrupted before refresh.
Innovation Solution
A semiconductor device architecture that includes multiple memory blocks with dedicated refresh control blocks to perform discontinuous smart refresh operations, alternating block control signals and generating refresh control pulse signals to manage refresh operations efficiently within the limited time, ensuring all memory banks are refreshed within the specified tRFC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capability is improved, but refresh time margin decreases
Solution Approach 1:
The memory device is divided into multiple memory blocks (first memory block, second memory block, etc.), each with dedicated refresh control logic. This segmentation allows parallel refresh operations across different blocks, enabling complete refresh of all memory units within the limited tRFC window even as total memory capacity increases.
Solution Approach 2:
The refresh operation is structured as periodic discontinuous refresh cycles, where different memory blocks are refreshed in alternating periods. The refresh control blocks generate periodic refresh pulse signals that activate different blocks at different times, ensuring all blocks receive refresh within the overall tRFC period through time-division multiplexing.
2Reliability
If smart refresh operation is added, then data integrity is improved, but device complexity increases
Solution Approach 1:
The refresh control functionality is segmented into multiple dedicated refresh control blocks, each responsible for specific memory blocks. This distribution of control logic reduces the complexity burden on any single control unit while collectively achieving comprehensive smart refresh coverage across all memory units.
Solution Approach 2:
The system performs preliminary detection of frequently activated word lines and pre-identifies target memory units that require refresh. This preliminary action enables the smart refresh operation to focus resources on vulnerable memory cells before data corruption occurs, improving data integrity without requiring complex real-time monitoring during the refresh execution phase.
Data Source
AI summary
A semiconductor device includes a first memory block, a second memory block, a first refresh control block for generating a first block control signal and a second block control signal in response to a refresh pulse signal, a second refresh control block for generating a first refresh control pulse signal and a second refresh control pulse signal corresponding to a first refresh operation section of the first memory block and a second refresh operation section of the second memory block, respectively, in response to the refresh pulse signal and the first and second block control signals, and a third refresh control block for controlling the first and second memory blocks so that a first refresh operation of the first memory block and a second refresh operation of the second memory block are discontinuously performed in response to the first and second refresh control pulse signals.