Memory Device Programmable Refresh Modes
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Solution Overview
Problem
Memory devices with short data retention times are typically discarded as failures due to insufficient refresh operations, as they cannot maintain data storage effectively without frequent and efficient recharge processes.
Innovation Solution
A memory device with a refresh control unit that switches between different modes of refresh operations, allowing a variable number of memory blocks to be refreshed at once based on additional refresh information, enabling more efficient data retention and preventing failure processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory device has short data retention time, then it cannot maintain data storage effectively, but increasing refresh frequency increases power consumption and operational complexity
Solution Approach 1:
The patent implements dynamic refresh control by switching between first and second refresh modes based on operational conditions. The refresh control unit dynamically adjusts the number of memory blocks refreshed per command (first number vs. second number where second < first), transforming the static refresh process into a dynamic adaptive system that resolves the contradiction between reliability and complexity.
Solution Approach 2:
The patent changes the parameter of refresh block count from a fixed value to a variable that can be adjusted between two modes. By storing additional refresh information and switching between different refresh block quantities, the system adapts the refresh operation intensity to match actual data retention needs, improving reliability while managing complexity.
2Reliability
If all memory blocks are refreshed at once, then data retention is maintained, but power consumption and operational overhead increase
Solution Approach 1:
The patent segments the refresh operation into different modes with different block counts. Instead of always refreshing all memory blocks, the system divides refresh operations into a first mode (refreshing first number of blocks) and a second mode (refreshing second number of blocks where second < first). This segmentation allows selective refresh of only necessary memory blocks, reducing overall power consumption while maintaining data retention.
Solution Approach 2:
The patent applies partial action by refreshing only a portion of memory blocks in the second mode rather than all blocks. When additional refresh information is deactivated, the system performs sufficient refresh on a reduced set of blocks, achieving acceptable data retention with lower power consumption by doing just enough refresh rather than exhaustive refresh of all blocks.
3Reliability
If refresh commands are applied frequently, then data loss is prevented, but operational efficiency and productivity decrease
Solution Approach 1:
The patent makes the refresh command frequency and block count dynamic rather than static. The refresh control unit switches between first and second modes based on the state of additional refresh information, allowing the system to adjust refresh intensity to match actual data retention requirements. This dynamic approach prevents unnecessary frequent refreshes, improving operational efficiency while maintaining data integrity.
Solution Approach 2:
The patent changes the refresh operation parameter from a fixed high-frequency approach to a variable approach. By storing additional refresh information and adjusting the number of blocks refreshed per command between two modes, the system optimizes the balance between data integrity and operational efficiency, avoiding excessive refresh operations that would reduce productivity.
Data Source
AI summary
A memory device includes a plurality of memory blocks, a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number, a storage circuit configured to store additional refresh information, and a refresh control unit configured to control the second number of memory blocks to be refreshed at a time whenever a refresh command is applied when the additional refresh information is deactivated, and to control the first number of memory blocks to be refreshed at a time whenever the refresh command is applied when the additional refresh information is activated in a case in which the second mode is set by the setting circuit.