Memory Refresh Control Circuit for Current Distribution
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Solution Overview
Problem
As memory capacity increases, the number of rows that need to be refreshed during a refresh cycle time (tRFC) also increases, making it challenging to efficiently refresh a plurality of memory areas within the given time, which results in high current consumption and difficulty in maintaining the specified tRFC value.
Innovation Solution
A method that involves generating refresh control signals sequentially, using a control signal generation circuit to delay and activate refresh signals across multiple memory banks, and a refresh stop circuit to manage the refresh operation, allowing for overlapping activation sections of refresh control signals to distribute current consumption evenly and reduce the time required for the refresh operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory rows is increased to expand memory capacity, then the memory capacity is improved, but the number of rows requiring refresh within a fixed refresh cycle time increases, causing the refresh operation to exceed the available time and increasing current consumption
Solution Approach 1:
The memory banks are divided into multiple groups, and each group is assigned a dedicated refresh control signal. This segmentation allows parallel refresh operations across different groups, reducing the total time required to refresh all memory rows while maintaining the ability to handle increased memory capacity.
Solution Approach 2:
The control signal generation circuit proactively generates staggered refresh control signals in advance, with each signal activated at a different time. This preliminary timing arrangement ensures that refresh operations are distributed evenly throughout the refresh cycle, preventing time conflicts and current consumption spikes.
2Loss of time
If multiple memory rows are refreshed simultaneously to reduce refresh time, then the refresh cycle time is improved, but the current consumption increases due to the simultaneous activation of multiple refresh operations
Solution Approach 1:
Refresh operations are segmented into multiple groups, each controlled by a separate refresh control signal. This segmentation distributes the current draw across different time intervals, preventing simultaneous high-current operations while still achieving efficient refresh coverage through parallel group processing.
Solution Approach 2:
The control signal generation circuit creates periodic refresh control signals with staggered activation times. Each group of memory banks receives refresh commands at different periodic intervals, spreading the current consumption evenly over time while maintaining continuous refresh coverage across all memory rows.
3Device complexity
If the refresh control signals are activated at the same time to simplify control logic, then the device complexity is reduced, but the refresh operation cannot complete within the specified refresh cycle time for large memory capacities
Solution Approach 1:
The control logic is segmented into multiple independent signal generation paths, each handling a specific group of memory banks. This segmentation maintains relatively simple control logic for each path while the collective operation of all paths achieves the required refresh coverage within the specified time, solving the contradiction between simplicity and performance.
Solution Approach 2:
The control signal generation circuit is designed to pre-establish the timing relationships between multiple refresh control signals. This preliminary configuration of staggered activation times is built into the control logic, allowing simultaneous generation of multiple signals without requiring complex runtime coordination, thus maintaining simplicity while achieving timely refresh completion.
Data Source
AI summary
A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.