Memory Block Refresh Erase for Low-Stress Threshold Recovery

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Solution Overview

Problem

Conventional erase operations in non-volatile memory devices lead to programming disturbances due to residual holes trapped in the wordline or channel, causing threshold voltage shifts and read margin issues, which are not effectively addressed by existing methods that involve waiting periods or additional erase operations.

Innovation Solution

Implementing a low stress refresh erase method that includes a first erase operation followed by periodic erase detection, and if necessary, a second erase operation without a pre-programming pulse and with a smaller erase voltage, to reduce the number of trapped holes and minimize programming disturbances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional erase operations are performed in non-volatile memory devices, then data retention is achieved, but programming disturbances occur due to residual holes trapped in the wordline or channel causing threshold voltage shifts

Engineering Contradiction:

Improvedata retentionVSAvoidprogramming disturbances

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A read operation is performed before the program operation to detect and correct threshold voltage shifts caused by residual holes from the erase operation. This preliminary detection action identifies disturbed cells that need re-erasing before programming, preventing programming disturbances from occurring

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system performs a read operation after erase and before program to detect threshold voltage shifts, then uses this feedback information to determine whether re-erase is needed. This feedback mechanism dynamically adjusts the erase process based on actual cell state, eliminating programming disturbances while maintaining data retention

Inventive Principle:

Principle #23Feedback

2Object-generated harmful factors

If waiting periods or additional erase operations are performed to address residual holes, then programming disturbances are reduced, but operation time increases

Engineering Contradiction:

Improveprogramming disturbancesVSAvoidoperation time

Core Design Contradiction:

Object-generated harmful factorsVSLoss of time

Solution Approach 1:

Instead of using fixed waiting periods or blanket additional erase operations, the system performs a targeted read operation to detect actual threshold voltage shifts. This feedback-based approach only triggers re-erase when necessary, reducing programming disturbances without incurring unnecessary time delays from always performing additional operations

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system uses the existing read capability of the memory device to self-diagnose threshold voltage shifts and determine whether re-erase is needed. This self-service approach eliminates the need for external monitoring or fixed timing protocols, reducing operation time while effectively addressing programming disturbances

Inventive Principle:

Principle #25Self-service

3Reliability

If multiple erase operations are performed to ensure complete erasure, then erase reliability is improved, but the number of program/erase cycles increases causing wear

Engineering Contradiction:

Improveerase reliabilityVSAvoidmemory cell life cycle

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The system performs a read operation after erase to verify completion and detect threshold voltage shifts. This feedback mechanism determines whether an additional program/erase cycle is actually needed, achieving erase reliability through verification rather than relying on fixed multiple erase cycles, thereby extending memory cell life

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system replaces the mechanical approach of repeatedly performing program/erase cycles with a detection-based approach using read operations. Instead of blindly performing multiple erases, the system uses electrical detection to verify erase completion and identify cells needing re-erase, reducing unnecessary wear on memory cells while maintaining erase reliability

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250342891A1Low stress refresh erase in a memory device

Publication Date: 2025.11.06 MICRON TECHNOLOGY INC

AI summary

A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.