Memory Program Refresh Using GIDL to Tighten Read Windows
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Solution Overview
Problem
Existing memory devices face challenges in storing additional bits per cell due to narrow threshold voltage distributions and reduced read window budgets, making it difficult to increase bit storage without compromising reliability.
Innovation Solution
Implementing program refresh with gate-induced drain leakage (GIDL) to tighten threshold voltage distributions and recover read window budgets by applying controlled bias voltages to generate positive charge carriers to neutralize negative charge carriers, thereby enhancing memory cell programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional programming methods are used to increase bits per cell, then storage capacity increases, but threshold voltage distributions become narrow and read window budgets decrease
Solution Approach 1:
The patent applies parameter changes by modifying the voltage distribution characteristics through GIDL operations. By controlling the voltage applied to the control gate and drain, the method adjusts the threshold voltage distribution width, thereby expanding the read window budget while maintaining increased bits per cell storage capacity.
Solution Approach 2:
The patent converts the typically harmful GIDL effect, which causes leakage current and threshold voltage shifts, into a beneficial operation for refreshing and redistributing charge carriers. By deliberately inducing GIDL under controlled conditions, the method tightens threshold voltage distributions and recovers read window budgets, transforming a detrimental phenomenon into a useful mechanism for maintaining reliability in high-density storage.
2Quantity of substance
If more bits are stored per cell, then storage density increases, but threshold voltage distributions narrow making differentiation difficult
Solution Approach 1:
The patent uses parameter changes by adjusting the voltage conditions during GIDL operations to control the spread and width of threshold voltage distributions. This allows differentiated voltage levels for multiple bits per cell while maintaining sufficient separation between distribution edges for reliable reading.
Solution Approach 2:
The patent implements feedback through iterative GIDL refresh operations that monitor and adjust charge carrier distributions. By repeatedly applying controlled GIDL and measuring the resulting threshold voltage distributions, the system optimizes the separation between voltage levels representing different bit states, thereby improving measurement precision for multi-bit cells.
3Reliability
If program refresh operations are performed to maintain data integrity, then reliability improves, but disturb effects such as erase and program disturb increase
Solution Approach 1:
The patent applies local quality by performing GIDL refresh operations selectively on specific word lines or memory regions that require refreshing, rather than uniformly across the entire memory array. This localized approach maintains data integrity in affected regions while minimizing disturb effects on neighboring cells that do not require refreshing.
Solution Approach 2:
The patent uses partial action by applying GIDL operations with controlled voltage magnitudes and durations that are sufficient to refresh charge carriers but not excessive enough to cause significant disturb effects. By optimizing the refresh parameters to the minimum necessary level, the method maintains reliability while reducing harmful side effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases read margin and reliability, allowing for more bits to be stored per cell while minimizing disturb effects such as erase and program disturb.
Implementation Method 1
program refresh with gate-induced drain leakage (GIDL) to tighten threshold voltage distributions and recover read window budgets by applying controlled bias voltages to generate positive charge carriers to neutralize negative charge carriers
Data Source
AI summary
A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing gate-induced drain leakage (GIDL) to be generated during a seeding operation of a program refresh operation, and causing, during the seeding operation, positive charge carriers generated by the GIDL to be transported to neutralize negative charge carriers generated by the program refresh operation.


