Memory Program Refresh Using ALP and GIDL Seeding
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Solution Overview
Problem
Existing memory devices face challenges in efficiently increasing read window budget (RWB) and maintaining data retention after manufacturing, particularly due to high temperature processes like infrared reflow, which can lead to data loss and require additional time and resources for program refresh operations.
Innovation Solution
Implementing an all levels program (ALP) operation combined with gate-induced drain leakage (GIDL) seed and wordline staggered discharge (WSD) program verify operations to refresh data, including a first phase of ramping wordline voltage and a second phase of programming levels, with integrated GIDL and WSD to neutralize charge carriers and adjust discharge timings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional programming operations are used, then programming time is reduced, but read window budget (RWB) increases insufficiently and reliability deteriorates
Solution Approach 1:
The programming operation is divided into multiple distinct phases: a first programming phase that programs memory cells to a first data state, and a second programming phase that programs memory cells to a second data state. This segmentation allows each phase to be optimized independently, achieving both fast programming and sufficient read window budget enhancement for reliable data retention.
Solution Approach 2:
The first programming phase is performed as a preliminary action before the second programming phase. By pre-programming memory cells to the first data state with appropriate voltage conditions, the subsequent second programming phase can more effectively establish the final data state, thereby achieving both speed and reliability goals.
2Ease of manufacture
If infrared reflow process is applied, then manufacturing completeness is improved, but data loss occurs and additional qualification resources are required
Solution Approach 1:
The dual-phase programming operation serves as a cushioning mechanism against data loss from infrared reflow. By establishing data in two distinct phases with different voltage conditions, the method creates redundancy that protects against potential data corruption during manufacturing processes like infrared reflow, eliminating the need for additional qualification resources.
Solution Approach 2:
The invention changes the programming voltage parameters between the first and second programming phases. The first phase uses one set of voltage conditions while the second phase uses different voltage conditions, creating distinct data states that are more resilient to manufacturing variations and thermal processes like infrared reflow.
3Reliability
If programming voltage is increased to enhance read margin, then read reliability is improved, but disturb effects increase
Solution Approach 1:
The invention applies different voltage conditions to different phases of programming. The first programming phase uses specific voltage conditions optimized for initial programming, while the second programming phase uses different voltage conditions optimized for enhancing read margin. This local optimization of voltage parameters achieves high read reliability without excessive disturb effects.
Solution Approach 2:
The programming operation is performed in periodic distinct phases rather than as a single continuous operation. The first programming phase and second programming phase are separated in time and use different voltage parameters, allowing the system to achieve enhanced read margin while controlling disturb effects through periodic voltage application patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory device performance by improving RWB, reducing programming time, energy consumption, and write amplification, while ensuring reliable data retention and compliance with auto retention and cross-temperature reliability requirements.
Implementation Method 1
integrated with gate-induced drain leakage (GIDL) seed
Implementation Method 2
optimizing programming by floating pillars
Implementation Method 3
wordline staggered discharge (WSD) program verify operations
Data Source
AI summary
A memory device includes a memory array including a plurality of wordlines; and at least one string of cells, each cell of the at least one string of cells being addressable by a respective wordline of the plurality of wordlines; and control logic, operatively coupled with the memory array, to perform operations including: initializing a loop of a program refresh operation; causing a set of memory cells addressable by a selected wordline, of the plurality of wordlines, to be programmed during the loop by: causing, during a first time period of a program operation, a seed operation to be performed on the set of memory cells; causing, during a second time period of the program operation, a ramping wordline voltage to be applied to the set of memory cells of the selected wordline; causing, during the second time period, a disconnection of a set of pillars associated with the set of memory cells from a voltage supply and a ground voltage, wherein each pillar corresponds to a respective programming level of a set of programming levels; causing, during a third time period of the program operation, a program pulse to be applied to the set of memory cells, wherein the program pulse programs each programming level of the set of programming levels associated with the set of memory cells; and causing, during a program verify time period of the program operation, a program verify operation performed on the set of memory cells.