Semiconductor Memory Refresh Control Circuit
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Solution Overview
Problem
In semiconductor devices requiring refresh operations, such as DRAMs, the concentrated refresh method often results in memory cells with shorter information retaining times being intermittently refreshed, leading to potential data loss due to extended refresh intervals, especially when transitioning between auto refresh and self refresh modes.
Innovation Solution
A semiconductor device design that includes a refresh-command generating circuit, a refresh address counter, a self refresh counter, and a control circuit to manage interrupt signals, allowing for frequent refresh operations on relief addresses with shorter information retaining times, even during entry and exit from self refresh mode, and preventing interruptions during auto refresh commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the concentrated refresh method is used to issue auto refresh commands 8192 times within 64 msec, then all memory cells can be refreshed within the standard period, but memory cells with shorter information retaining times experience extended refresh intervals and potential data loss
Solution Approach 1:
The patent segments the refresh operation into two distinct parts: (1) automatic refresh for normal memory cells using the refresh address counter, and (2) forced refresh for specific memory cells with shorter retention times using a forced refresh register. This segmentation allows different refresh strategies to be applied to different cell types simultaneously, ensuring that short-retention cells receive frequent refreshes without preventing the overall refresh cycle from completing within 64 msec.
Solution Approach 2:
The system performs preliminary identification and registration of memory cells with shorter information retaining times in the forced refresh register before the refresh cycle begins. This preliminary action enables the control logic to proactively interrupt the refresh address counter and force refresh operations on specific cells at appropriate intervals, preventing data loss before it occurs rather than reacting after the problem arises.
2Reliability
If the refresh operation is periodically interrupted for memory cells with shorter information retaining time, then those cells can be frequently refreshed, but the refresh operation cannot be completed for all refresh addresses by issuing auto refresh commands 8192 times
Solution Approach 1:
The patent implements a feedback mechanism where the control logic continuously monitors the state of the refresh address counter and the forced refresh register. When a forced refresh is executed, the system receives feedback that the refresh address counter has been interrupted, and accordingly issues additional auto refresh commands to ensure all 8192 addresses are eventually refreshed. This feedback loop maintains refresh completeness while adapting to the dynamic requirements of short-retention cells.
Solution Approach 2:
The system dynamically changes the refresh operation parameters by selectively enabling or disabling interruptions of the refresh address counter based on the state of the forced refresh register. When short-retention cells need refresh, the counter is interrupted and the refresh count parameter is adjusted; when they don't need refresh, normal operation continues. This parameter adaptation allows the system to maintain high efficiency while ensuring reliability.
3Reliability
If the concentrated refresh method issues auto refresh commands in a fixed period, then the refresh interval can be controlled, but memory cells not refreshed during command issuance periods experience doubled refresh intervals
Solution Approach 1:
The patent introduces dynamic control of the refresh process by allowing the refresh address counter to be selectively interrupted and restarted based on forced refresh requirements. This dynamic adjustment ensures that cells requiring frequent refresh (short-retention cells) receive timely updates, while the overall refresh schedule remains flexible enough to prevent excessive delays for other cells. The system adapts the refresh timing in real-time rather than following a rigid fixed schedule.
Data Source
AI summary
A semiconductor device includes a first circuit that generates a self refresh signal in a predetermined cycle asynchronous with a cycle set externally, a second circuit that generates a refresh address in response to the self refresh signal and updates the refresh address and outputs the refresh address, a third circuit that retains a relief address, a fourth circuit that counts number of generation of the self refresh signal and activates an interrupt signal when a count of the number of generation reaches a predetermined count, a fifth circuit that specifies the refresh address when the interrupt signal is in an inactive state and specifies the relief address when the interrupt signal is in an active state, and a sixth circuit that performs a refresh operation on memory cells specified by the selected refresh address or the relief address. The second circuit temporarily stops updating the refresh address in response to activation of the interrupt signal.