Semiconductor Memory Refresh Control Circuit Test Efficiency
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Solution Overview
Problem
Conventional pseudo SRAMs face inefficiencies in testing due to the necessity of performing refresh operations during access cycles, which prolongs access time and reduces test efficiency, as refresh operations are often unnecessary and conflict with external access requests.
Innovation Solution
A semiconductor memory design that includes an access control circuit and a refresh control circuit, allowing for a test refresh request signal to be generated only during a test mode and using a data mask terminal as a multipurpose terminal for both data and refresh mask signals, thereby dispensing with a dedicated refresh mask terminal and optimizing access cycle times based on the need for refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a refresh operation is executed during an access cycle in test mode, then the refresh operation can be synchronized with the access command, but the access cycle time cannot be shortened and test efficiency deteriorates
Solution Approach 1:
The patent applies dynamics by making the refresh operation conditional rather than fixed. The refresh control circuit dynamically adjusts whether to execute a refresh operation based on the refresh mask signal state. When the refresh mask signal is at the valid level, the refresh operation is prohibited, allowing the access cycle time to be shortened. When the refresh mask signal is at the invalid level, the refresh operation is executed in synchronization with the access command. This dynamic control resolves the contradiction between ensuring refresh operation reliability and improving test efficiency.
2Ease of operation
If a dedicated terminal for receiving refresh mask signal is provided, then the refresh operation control is simplified, but the chip size increases
Solution Approach 1:
The patent applies universality by making the data mask terminal serve multiple functions. During normal operation mode, the data mask terminal receives the data mask signal for masking data signals. During test mode, the same data mask terminal receives the refresh mask signal for controlling refresh operations. This multi-functionality eliminates the need for a dedicated refresh mask terminal, thereby preventing chip size increase while maintaining simplified refresh control functionality.
Data Source
AI summary
A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command so as to execute a refresh operation of the memory cells when a refresh mask signal is at an invalid level. Also, the refresh control circuit prohibits generation of the test refresh request signal when the refresh mask signal is at a valid level. The test refresh request signal is generated or prohibited from being generated according to the level of the refresh mask signal. Thus, only a refresh operation needed for a test can be executed, and hence test efficiency can be improved.