Memory Device Refresh Tracking via Mode Register
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Solution Overview
Problem
In volatile memory devices like DRAM, the frequent refresh operations to prevent data loss due to leakage currents make it difficult to track and verify the accuracy of refresh operations, especially when combined with row hammering effects, which can lead to data corruption and reduce analysis accuracy.
Innovation Solution
A memory device and system that includes a control logic with a mode register to store and output bank and row addresses during refresh operations, allowing for tracking of refresh addresses and improving the accuracy of operation verification and defect analysis by distinguishing between normal and target refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are frequently performed to prevent data loss, then data reliability is improved, but tracking and verification of refresh operations becomes difficult
Solution Approach 1:
A mode register is introduced as an intermediary component between the refresh operation and the external verification system. The mode register stores and outputs bank address and row address information during refresh operations, enabling external tracking and verification without interfering with the frequent refresh operations needed for data reliability.
2Measurement precision
If mode register write commands are generated for every refresh operation, then tracking accuracy is improved, but device complexity and operation overhead increase
Solution Approach 1:
Instead of generating mode register write commands for every single refresh operation, the system generates these commands selectively based on operational mode. In normal mode, internal mode register write commands are generated automatically. In test mode, the system can choose to generate these commands only for specific refresh operations that need verification, reducing unnecessary overhead while maintaining tracking accuracy where needed.
3Measurement precision
If all refresh operations are tracked and verified, then analysis accuracy is improved, but processing time and resource consumption increase
Solution Approach 1:
The system dynamically adjusts its tracking and verification behavior based on the operational mode. In normal operational mode, the system performs refresh operations with minimal tracking overhead. In test mode, the system enhances tracking and verification for specific operations. This dynamic adaptation allows the system to maintain analysis accuracy when needed while minimizing processing time during normal operation.
Data Source
AI summary
According to an embodiment, a memory device includes a memory cell array including a plurality of memory cells; and a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.