Semiconductor Memory Refresh Control Circuit for Data Retention Stability

Solution Overview

Problem

Current semiconductor memory apparatuses face challenges in stabilizing data retention due to the need for refresh operations in volatile memory, which can be inefficient and prone to errors, especially when handling multiple banks simultaneously.

Innovation Solution

The semiconductor memory apparatus incorporates a refresh mode selection circuit and control circuits to generate signals for single bank and all bank refresh modes, enabling efficient row address increase signals to ensure stable data retention across all designated banks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh operations are performed for all banks simultaneously, then data retention stability is improved, but device complexity and control difficulty increase

Engineering Contradiction:

Improvedata retention stabilityVSAvoidcontrol circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The refresh operation is segmented into two distinct modes: single bank refresh mode and all bank refresh mode. The refresh mode selection circuit divides the refresh control into separate pathways, allowing independent optimization of each mode. In single bank mode, refresh is performed on one bank at a time with simpler control logic, while all bank mode enables simultaneous refresh of multiple banks when needed for enhanced stability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between single bank refresh mode and all bank refresh mode based on operational requirements. The refresh mode selection circuit responds to external commands and refresh control signals to adaptively select the appropriate refresh strategy, enabling the system to optimize between simplicity and stability as conditions change.

Inventive Principle:

Principle #15Dynamics

2Device complexity

If single bank refresh mode is used, then device complexity is reduced, but data retention reliability deteriorates

Engineering Contradiction:

Improvecontrol circuit complexityVSAvoiddata retention stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The refresh operation is segmented into two distinct modes: single bank refresh mode and all bank refresh mode. The refresh mode selection circuit divides the refresh control into separate pathways, allowing independent optimization of each mode. In single bank mode, refresh is performed on one bank at a time with simpler control logic, while all bank mode enables simultaneous refresh of multiple banks when needed for enhanced stability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between single bank refresh mode and all bank refresh mode based on operational requirements. The refresh mode selection circuit responds to external commands and refresh control signals to adaptively select the appropriate refresh strategy, enabling the system to optimize between simplicity and stability as conditions change.

Inventive Principle:

Principle #15Dynamics

3Speed

If row address increase signal is enabled early, then refresh operation speed is improved, but data retention accuracy deteriorates

Engineering Contradiction:

Improverefresh operation speedVSAvoidrow address accuracy

Core Design Contradiction:

SpeedVSMeasurement precision

Solution Approach 1:

The row address increase signal is enabled only after all preset banks designated by the bank address are activated. This preliminary condition ensures that the complete set of banks has been properly initialized and activated before the row address begins to increase, preventing premature address transitions that could lead to data access errors.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The first refresh mode control circuit monitors the activation status of all preset banks and uses this feedback to control the enabling of the row address increase signal. The circuit waits for confirmation that all banks are activated before allowing the row address to increase, ensuring synchronized operation and accurate address tracking throughout the refresh process.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9548100B2Semiconductor memory apparatus performing a refresh operation

Publication Date: 2017.01.17 SK HYNIX INC

AI summary

A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.