Memory Controller Prioritizing Refresh of High Bit Error Rate Blocks
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Solution Overview
Problem
Memory systems face increased latency due to the need to refresh pre-loaded memory blocks with high bit error rates at power-on, which can lead to system failure if not addressed promptly, while refreshing all blocks simultaneously prolongs the power-up duration.
Innovation Solution
A memory system prioritizes refreshing memory blocks with high bit error rates at power-on and schedules the refresh of blocks with lower error rates for later times, based on their bit error rates and system resources, to minimize latency and ensure system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory blocks are refreshed simultaneously at power-on, then all blocks are ensured to be error-free, but the power-up duration is prolonged
Solution Approach 1:
The patent segments the memory blocks into different priority groups (high priority and low priority blocks) based on their bit error rates. High priority blocks with higher error rates are refreshed first, while low priority blocks with lower error rates are refreshed later. This segmentation allows the system to achieve reliable error correction for critical blocks without waiting to refresh all blocks simultaneously, thus reducing power-up duration while maintaining reliability.
2Reliability
If memory blocks with high bit error rates are refreshed immediately, then system reliability is improved, but system latency increases due to blocking other operations
Solution Approach 1:
The patent performs preliminary actions by scanning and identifying blocks with high bit error rates before initiating the refresh process. The controller proactively detects error rates and pre-determines refresh priorities, allowing the system to prepare refresh operations in advance without blocking other critical operations. This preliminary identification enables the system to maintain reliability by targeting high-error blocks while minimizing latency through non-blocking refresh scheduling.
3Measurement precision
If the controller scans all blocks to determine bit error rates, then accurate prioritization is achieved, but the scanning process adds to the power-up time
Solution Approach 1:
The patent applies partial action by scanning only a subset of memory blocks (specifically, blocks that require refresh based on their error rates) rather than systematically scanning all blocks. The controller selectively identifies and scans blocks with high bit error rates for prioritization, while blocks with lower error rates are handled through different mechanisms. This partial scanning approach maintains sufficient measurement precision for accurate prioritization of critical blocks while significantly reducing the time required compared to a complete scan of all blocks.
Data Source
AI summary
Methods, systems, and devices for prioritizing refresh operations of a memory system are described. In some instances, a memory system may refresh one or more production state awareness (PSA) blocks at power-on. In some cases, the PSA blocks that are refreshed may have relatively high bit error rates (BERs). For example, PSA blocks with relatively high BERs that are not refreshed may increase the risk of system failure or malfunction. Other PSA blocks may not be refreshed at power-on, and may instead be refreshed at a later time based on one or more criteria in order to prioritize refreshing the PSA blocks having relatively high BERs.