Memory Cell Refresh by Programming Level for Error Recovery
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Solution Overview
Problem
Existing memory sub-systems face inefficiencies in data refresh operations due to performing refresh operations on all memory cells without considering the varying error rates across different programming levels, leading to increased resource consumption, latency, and reduced reliability.
Innovation Solution
Perform data refresh operations on a per-programming-level basis, selectively targeting memory cells with high error rates and avoiding those with low error rates to reduce computing resources, energy consumption, and duration of refresh cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data refresh operations are performed on all memory cells uniformly, then data reliability is maintained, but resource consumption increases and refresh duration extends
Solution Approach 1:
The patent segments the memory device into multiple programming level groups (first group with first programming levels, second group with second programming levels) and performs refresh operations on each group separately. This segmentation allows the system to apply different refresh strategies to different programming level groups, refreshing only those groups that require it based on their specific error characteristics, thereby improving refresh efficiency while maintaining data reliability.
Solution Approach 2:
The patent implements local quality by determining error rates specifically for each programming level group and applying refresh operations selectively based on these local error characteristics. Instead of uniform refresh across all memory cells, the system identifies which programming level groups have higher error rates and targets refresh operations to those specific local regions, optimizing resource utilization while maintaining reliability where needed.
2Reliability
If data refresh operations are performed on all memory cells, then data integrity is maintained, but energy consumption increases
Solution Approach 1:
The patent applies partial action by performing refresh operations only on specific programming level groups that require refreshing, rather than on all memory cells. The system determines error rates for different programming level groups and selectively refreshes only those groups with higher error rates, thereby reducing overall energy consumption while maintaining data integrity for the critical portions of stored data.
3Reliability
If data refresh operations are performed on all memory cells, then reliability is maintained, but refresh cycle duration increases
Solution Approach 1:
The patent segments the refresh operation into multiple smaller operations targeting different programming level groups separately. By dividing the memory device into first and second programming level groups and refreshing them in sequence rather than simultaneously refreshing all cells, the system reduces the duration of each individual refresh cycle while maintaining overall data reliability through comprehensive coverage of all groups.
Solution Approach 2:
The patent applies partial action by performing refresh operations only on programming level groups that require refreshing based on their error rate characteristics. This selective approach reduces the total number of cells subjected to refresh operations in each cycle, thereby reducing refresh cycle duration while maintaining data reliability for the groups that need refreshing.
Data Source
AI summary
A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including writing data to an MU of the memory device and performing one or more scan operations on the MU to determine an aggregate value of a data state metric reflective of an amount of erroneous memory cells in the MU. The operations can include determining whether a value of the data state metric reflective of a specified set of erroneous memory cells in the MU satisfies a criterion and identifying a target programming level to which at least one erroneous memory cell was originally programmed. They can also include reprogramming the at least one erroneous memory cell to the target programming level.