Memory Device Refresh Rate Selection for MBIST
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in efficiently performing memory built-in self-tests (MBIST) while minimizing downtime and ensuring reliability, particularly in applications requiring different refresh rates for normal operations and MBIST testing.
Innovation Solution
The implementation of a refresh rate selection mechanism in memory devices, allowing for the identification of test refresh rates stored in mode registers, enables MBIST testing to be performed concurrently with memory cell refreshing, optimizing test time and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single refresh rate is used for both normal operations and MBIST testing, then device complexity is reduced, but test time increases and productivity decreases
Solution Approach 1:
The patent implements dynamic refresh rate selection by providing multiple refresh rate options (first refresh rate for normal operations, second refresh rate for MBIST testing) that can be selected based on the operational mode. The memory device includes a refresh rate selection mechanism that switches between different refresh rates depending on whether the device is performing normal memory operations or MBIST operations, thereby optimizing test time without permanently increasing device complexity.
Solution Approach 2:
The patent changes the refresh rate parameter from a fixed single value to a selectable set of values. By defining different refresh rate parameters (first refresh rate and second refresh rate) and selecting the appropriate one based on operational context, the system achieves faster MBIST testing while maintaining flexibility in normal operations.
2Productivity
If MBIST testing is performed without concurrent refreshing, then refresh operations are simplified, but downtime increases and productivity decreases
Solution Approach 1:
The patent enables continuous operation during MBIST testing by performing memory cell refreshing concurrently with MBIST test operations. The refresh rate is adjusted to allow both refreshing and testing to occur simultaneously without interfering with each other, thereby eliminating downtime and improving productivity.
Solution Approach 2:
The patent performs preliminary configuration of the refresh rate selection mechanism to prepare the memory device for concurrent MBIST testing and refreshing operations. By pre-configuring the appropriate refresh rate and selection logic, the system ensures that when MBIST testing is initiated, the device is already prepared to execute both operations simultaneously.
3Loss of time
If refresh rate is optimized for MBIST testing, then test time is reduced, but normal operation performance may be affected
Solution Approach 1:
The patent applies local quality by providing different refresh rate optimizations for different operational contexts. The first refresh rate is optimized for normal memory operations, while the second refresh rate is optimized specifically for MBIST testing. The refresh rate selection mechanism selects the appropriate refresh rate based on the current operational context, ensuring optimal performance for each specific application.
Solution Approach 2:
The patent implements a universal refresh rate selection mechanism that serves multiple functions: it supports both normal memory operations and MBIST testing operations with different refresh rate requirements. This multi-functional approach allows the same memory device to be optimized for different operational modes without requiring separate hardware configurations.
Data Source
AI summary
Implementations described herein relate to refresh rate selection for a memory built-in self-test. A memory device may read one or more bits, associated with the memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, a refresh rate to be used while performing the memory built-in self-test. The refresh rate may indicate a rate at which memory cells, to be tested by the memory built-in self-test, are to be refreshed while the memory built-in self-test is being performed. The memory device may perform the memory built-in self-test while refreshing the memory cells according to the refresh rate.