Memory Refresh Control Using Redundancy Cells for Row Hammer Defense
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Solution Overview
Problem
The row hammering phenomenon in semiconductor memory devices causes data loss in memory cells due to excessive activations of specific word lines, necessitating additional target refresh operations, which existing technologies have not effectively addressed.
Innovation Solution
A memory device design that allocates memory cells coupled to unused columns in a redundancy cell area for repairing row-hammer cells, utilizing a refresh control circuit to select target addresses based on access counting data and perform optimized refresh operations, while minimizing power consumption and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If target refresh operation is performed on row-hammer cells, then row hammer defense capability is improved, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters of refresh operations by identifying and refreshing only specific target rows that are susceptible to row hammering, rather than performing uniform refresh on all rows. This selective approach based on access counting data reduces the energy consumption while maintaining row hammer defense capability.
Solution Approach 2:
The patent applies different refresh strategies to different rows based on their vulnerability to row hammering. By using access counting data to identify target rows and performing refresh operations only on these specific rows rather than uniformly across all rows, the system optimizes power consumption while maintaining reliability.
2Measurement precision
If access counting data is stored in row-hammer cells, then target address selection accuracy is improved, but manufacturing complexity increases
Solution Approach 1:
The patent makes row-hammer cells serve multiple functions: they both store access counting data for target address selection and maintain their original memory cell functionality. This multi-functional approach improves target address selection accuracy without requiring entirely separate counting circuits, thereby limiting the increase in manufacturing complexity.
Solution Approach 2:
The patent combines the access counting function with the row-hammer cell storage function. By merging these functions into the same cell structure and using the same physical cells for both counting and storage, the system achieves accurate target address selection while avoiding the need for completely separate manufacturing processes.
3Productivity
If redundancy cells are allocated for row-hammer cells, then refresh efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic allocation of redundancy cells to row-hammer cells based on runtime conditions and access patterns. The system can flexibly configure which redundancy cells serve which row-hammer cells, allowing optimal refresh efficiency without requiring a fixed complex structure. This dynamic approach improves productivity while keeping device complexity manageable through software or control logic rather than hardwired complexity.
Data Source
AI summary
A memory device includes: a memory cell region including normal cells coupled to normal column selection lines, and row-hammer cells and redundancy cells respectively coupled to redundancy column selection lines; a repair control circuit configured to provide repair addresses and row-hammer flag signals, corresponding to repair information, according to a row address; and a column control circuit configured to activate at least one of the redundancy column selection lines according to the row-hammer flag signals or a comparison result of a column address and the repair addresses.