Memory Refresh Control for DRAM Rowhammer Defense
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Solution Overview
Problem
Volatile memory devices like DRAM are vulnerable to 'rowhammering' attacks, where repeatedly accessing a certain row can change data in adjacent rows, leading to data errors, especially in high-density memory systems without effective defense mechanisms.
Innovation Solution
A memory control device with a threshold generating circuit and attack defense circuit that sets thresholds based on module information, identifies aggressor row addresses, and initiates targeted refresh operations to protect against rowhammering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased, then storage capacity is improved, but vulnerability to rowhammering attacks increases
Solution Approach 1:
The patent implements a counter circuit that proactively counts and monitors access frequencies to each row address before a rowhammering attack can cause data corruption. By detecting excessive access patterns in advance and triggering refresh operations on adjacent rows preemptively, the system prevents harmful effects rather than reacting after damage occurs.
Solution Approach 2:
The patent introduces a refresh control circuit as an intermediary component between the memory controller and memory modules. This intermediary monitors access patterns, identifies aggressor rows through counting operations, and autonomously triggers refresh commands to protect victim rows, thereby mediating the harmful interaction between aggressive access patterns and vulnerable memory cells.
2Reliability
If row refresh operations are performed frequently, then data integrity is improved, but memory access speed deteriorates
Solution Approach 1:
Instead of uniformly refreshing all memory rows, the patent selectively applies refresh operations only to rows identified as victims of rowhammering attacks. The counter circuit monitors access patterns and triggers refresh commands only when specific rows exceed access thresholds, thereby performing partial refresh actions that maintain data integrity while minimizing disruption to overall memory access performance.
Solution Approach 2:
The patent implements periodic monitoring of row access patterns through counter circuits that continuously track access frequencies. Refresh operations are triggered periodically based on detected access patterns rather than continuously, allowing normal memory operations to proceed uninterrupted unless attack patterns are detected, thus balancing reliability and speed.
3Reliability
If attack defense function is added, then security against rowhammering is improved, but device complexity increases
Solution Approach 1:
The patent divides the attack defense functionality into distinct modular components: counter circuits for each row address, comparison logic for threshold evaluation, and refresh control logic. This segmentation allows the defense mechanism to be integrated incrementally and enables independent optimization of each component, reducing overall system complexity while maintaining comprehensive protection.
Solution Approach 2:
The refresh control circuit operates autonomously by self-monitoring access patterns through integrated counter circuits and automatically generating refresh commands when attack patterns are detected. This self-service capability eliminates the need for external intervention or complex centralized control, simplifying the overall device architecture while providing robust attack defense.
Data Source
AI summary
A memory control device includes a threshold generating circuit, which is configured to set a first threshold for a first memory module electrically coupled to the memory control device. This first threshold is based on information associated with the first memory module. An attack defense circuit is also provided, which is configured to count an input row address, and decide a row address whose count value exceeds the first threshold among row addresses of the first memory module as an aggressor row address.