Semiconductor Memory Refresh Signal Generator with Level Feedback Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices consume excessive power due to a fixed refresh period that does not account for variations in internal power levels, leading to suboptimal retention time and power usage.
Innovation Solution
A semiconductor memory device incorporating a level feedback circuit and refresh signal generator that adjusts the refresh period based on the voltage level of the internal power, allowing for dynamic adjustment of the refresh operation to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a fixed refresh period is used in conventional semiconductor memory devices, then the refresh operation is simple to implement, but power consumption increases because the refresh period cannot be optimized according to internal power level variations
Solution Approach 1:
The refresh period is made dynamic by adjusting it according to the internal power level (VBB voltage). The refresh control circuit monitors the internal power level and automatically adjusts the refresh period to match the current operating conditions, transitioning from a fixed static period to a dynamic adaptive period that optimizes power consumption based on real-time power level variations.
Solution Approach 2:
A feedback mechanism is introduced where the refresh control circuit monitors the internal power level (VBB) and uses this information to adjust the refresh period. The system continuously senses the power level and modifies the refresh timing accordingly, creating a closed-loop control system that optimizes power consumption while maintaining data retention requirements.
2Object-generated harmful factors
If the internal power level VBB is lowered to reduce off-current, then off-current decreases, but junction-current increases causing retention time to worsen
Solution Approach 1:
The system changes the refresh period parameter dynamically based on the internal power level. When VBB is lowered to reduce off-current, the system automatically adjusts the refresh period to ensure data retention requirements are still met. This parameter adjustment compensates for the increased junction-current effect, maintaining optimal data retention across different power operating points.
3Object-generated harmful factors
If the internal power level VBB is lowered to increase threshold voltage, then off-current is reduced, but junction-current increases leading to higher power consumption
Solution Approach 1:
The refresh control circuit implements feedback by monitoring the internal power level VBB and adjusting the refresh period accordingly. This feedback mechanism allows the system to respond to power level changes and optimize the refresh operation to minimize overall power consumption, preventing the scenario where reduced off-current is offset by increased junction-current power loss.
Data Source
AI summary
A semiconductor memory device includes a level feedback circuit and a refresh signal generator. The level feedback circuit outputs a bulk voltage applied to a cell transistor as a feedback signal. The refresh signal generator generates an internal refresh signal for driving a refresh operation at predetermined intervals during a self refresh mode. A period of the internal refresh signal is adjusted according to a voltage level of the feedback signal.