Memory Module Refresh Staggering for Signal Conflict Reduction
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Solution Overview
Problem
Existing memory systems face challenges in expanding memory space without increasing the number of chip select signals, leading to signal conflicts and high refresh current demands, especially in three-dimensional memory spaces.
Innovation Solution
The introduction of a third dimension in the address space using additional address bits allows for expanded memory access without increasing chip select signals, with a local memory controller staggering refresh operations to minimize signal conflicts and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional address bits are used to expand memory space, then memory capacity increases, but the number of chip select signals remains fixed leading to signal conflicts
Solution Approach 1:
The patent introduces a third dimension in the address space by utilizing additional address bits (e.g., A14) beyond the conventional two-dimensional address space defined by chip select signals and lower-order address bits. This allows memory expansion without increasing the number of chip select signals, as the third dimension is accessed through address bit combinations rather than additional physical signal lines.
Solution Approach 2:
The patent divides the expanded memory space into multiple logical ranks, where each logical rank corresponds to a set of physical ranks. This segmentation allows the memory controller to manage the third-dimensional address space in organized units, reducing signal conflicts by logically partitioning the memory access paths.
2Productivity
If refresh operations are performed on multiple physical ranks simultaneously, then memory refresh efficiency improves, but refresh current demand increases
Solution Approach 1:
The patent implements staggered refresh operations where refresh commands are issued periodically to different physical ranks at different times. Instead of refreshing all physical ranks simultaneously, the system cycles through the ranks in sequence, spreading the refresh current demand over time while still maintaining all ranks within their required refresh intervals.
Solution Approach 2:
The patent dynamically adjusts the refresh timing for different physical ranks based on their activation states and current operational requirements. The memory controller monitors which ranks are actively being accessed and schedules refresh operations for inactive ranks, optimizing the balance between refresh efficiency and current consumption.
Data Source
AI summary
A memory module according to certain aspects has a plurality of memory devices arranged into one or more logical ranks. Each logical rank may correspond to a set of at least two physical ranks. The memory module can include a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive a logical rank refresh command. In response, the circuit can initiate a first refresh operation for one or more first physical ranks and then initiate a second refresh operation for one or more second physical ranks. The memory module can further include a memory location storing a refresh time (tRFC) value accessible by the memory controller and based at least in part on a calculated maximum amount of time for refreshing the logical rank.