Memory Refresh Apparatus Staggered Control for Capacity
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Solution Overview
Problem
The increasing memory capacity requirements of computers, particularly servers, are hindered by the reduction in memory module slots due to industry trends like higher memory bus speeds and small form factor machines, while large capacity memory modules are cost-prohibitive, necessitating a cost-effective approach to enhance memory capacity.
Innovation Solution
A multiple memory circuit system where a plurality of smaller capacity memory circuits are used, with an interface circuit sending refresh control signals at different times to mimic a larger capacity memory circuit, effectively increasing memory capacity without the high cost of large monolithic modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large capacity monolithic memory circuits are used, then memory capacity is increased, but cost increases exponentially
Solution Approach 1:
The patent divides a large capacity memory system into multiple smaller capacity memory circuits (e.g., four 512Mb circuits to simulate 2Gb). Each smaller circuit is refreshed independently at different times, avoiding the exponential cost increase of using a single large monolithic memory circuit while achieving the same total capacity.
2Ease of manufacture
If multiple smaller capacity memory circuits are used, then cost is reduced, but device complexity increases
Solution Approach 1:
The patent combines multiple smaller memory circuits into a unified memory system that appears as a single large capacity circuit to the host system. The interface circuit merges the refresh operations of multiple smaller circuits, staggering them in time to reduce peak current while maintaining the illusion of a monolithic memory device.
Solution Approach 2:
The interface circuit acts as an intermediary between the host system and multiple smaller memory circuits. It translates refresh operations from the host into staggered refresh signals for individual memory circuits, managing the complexity internally while presenting a simple interface externally.
3Device complexity
If refresh control signals are sent simultaneously to all memory circuits, then refresh operation is simplified, but peak current increases
Solution Approach 1:
The patent implements periodic refresh operations where each memory circuit is refreshed at different time intervals. Instead of simultaneous refreshing, the interface circuit distributes refresh signals across different time periods, reducing the peak current drawn from the power supply while ensuring all circuits are refreshed within the required refresh period.
4Volume of moving object
If the number of memory module slots is reduced, then small form factor is achieved, but memory capacity expansion is limited
Solution Approach 1:
The patent nests multiple smaller memory circuits within a single memory module slot, creating a buffered stack configuration. The interface circuit manages these nested circuits to present a unified large capacity interface to the host, effectively increasing memory capacity without requiring additional physical slots.
Data Source
AI summary
An apparatus includes multiple first memory circuits, in which the multiple first memory circuits are positioned on at least one dual in-line memory module (DIMM). The apparatus includes an interface circuit operable to interface the first memory circuits with a system; present the first memory circuits to the system as one or more simulated second memory circuits; transmit, in response to receiving a first refresh control signal sent from the system to the one or more simulated memory circuits, multiple second refresh control signals to the first memory circuits; and apply a respective delay to each second refresh control signal transmitted to a corresponding first memory circuit. Each simulated second memory circuit has a corresponding second memory capacity that is greater than a first memory capacity of at least one of the first memory circuits.