Memory Refresh Table Management for Row-Hammer Mitigation
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Solution Overview
Problem
Existing memory devices face challenges in efficiently managing refresh operations to prevent row-hammer attacks, which can lead to data errors due to charge leakage between adjacent memory rows.
Innovation Solution
A memory device with a peripheral circuit that determines the existence of address information in a refresh table, performs refresh operations based on priority, and adjusts priority and storage locations within sub-tables to optimize refresh operations and reduce the risk of row-hammer attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed on all memory rows, then data errors caused by charge leakage are prevented, but operational efficiency deteriorates due to excessive refresh overhead
Solution Approach 1:
The patent applies local quality by performing refresh operations selectively on specific memory rows that are susceptible to row-hammer attacks rather than refreshing all memory rows uniformly. The refresh table stores address information of vulnerable memory rows, and the peripheral circuit identifies and refreshes only those rows based on address information matching, thereby improving operational efficiency while maintaining data reliability.
Solution Approach 2:
The patent implements preliminary action by pre-populating the refresh table with address information of memory rows that are likely to be affected by row-hammer attacks. This allows the system to proactively refresh vulnerable rows before data errors occur, rather than reacting to errors after they happen. The priority information in the refresh table enables the system to preemptively handle high-risk memory rows.
2Reliability
If refresh operations are performed frequently to prevent row-hammer attacks, then data reliability is improved, but energy consumption increases
Solution Approach 1:
The patent reduces energy consumption by applying refresh operations locally to only those memory rows identified in the refresh table, rather than performing global refresh operations on the entire memory array. The peripheral circuit compares address information from read commands with the refresh table and performs refresh operations only on matching rows, significantly reducing the total energy required for refresh operations while maintaining data reliability for vulnerable rows.
Solution Approach 2:
The patent applies partial action by performing refresh operations on a subset of memory rows that are most vulnerable to row-hammer attacks, as identified and stored in the refresh table. Instead of performing excessive refresh operations on all memory rows, the system performs partial refresh operations only where needed, reducing overall energy consumption while maintaining sufficient data reliability.
3Measurement precision
If the refresh table stores detailed address information for all memory rows, then refresh precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the refresh table into multiple sub-tables, where each sub-table stores address information for a specific portion of the memory array or for memory rows with similar characteristics. This segmentation reduces the complexity of managing a single large refresh table while maintaining precise tracking of vulnerable memory rows. The peripheral circuit can efficiently search and manage smaller sub-tables rather than a monolithic table.
Solution Approach 2:
The patent extracts only the essential address information and priority data needed for refresh operations into the refresh table, rather than storing complete metadata for all memory rows. The refresh table stores selectively extracted information (address information and priority) that is sufficient to identify and refresh vulnerable rows, reducing the overall complexity of the refresh management system while maintaining refresh precision for critical rows.
Data Source
AI summary
Examples of the present disclosure include a memory device, a control method thereof, and a memory system. The memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes memory rows each including memory cells coupled to one word line. The peripheral circuit is configured to determine, in response to a read command, whether address information same as first address information of a first memory row corresponding to the read command exists in a refresh table. The refresh table stores pieces of address information each corresponding to one of the memory rows. The peripheral circuit is configured to delete the address information same as the first address information from the refresh table in response to the address information same as the first address information existing in the refresh table.