Memory Refresh Timing Table for Access-Aware Data Retention

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Solution Overview

Problem

Semiconductor memory devices face issues with data loss due to current leakage, leading to increased operation time and current consumption due to frequent refresh operations required to maintain data integrity.

Innovation Solution

A memory device with a time table that stores the last access time and activation count for each word line, allowing independent refresh operations based on actual access times and activation frequencies, optimizing refresh operations and minimizing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh operations are performed frequently to prevent data loss, then data retention reliability is improved, but operation speed decreases and current consumption increases

Engineering Contradiction:
Improvedata retentionVSAvoidoperation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic refresh operations where the refresh timing and frequency are adjusted based on actual access patterns. The refresh control circuit determines refresh timing dynamically by comparing current time with stored last access times from the time table, rather than using fixed periodic intervals. This allows the system to adapt refresh operations to actual data retention needs, improving operation speed while maintaining reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of refresh interval timing based on access history. By storing last access times in the time table and calculating time differences, the system varies the refresh interval parameter dynamically. When the time difference exceeds a threshold, refresh is triggered; otherwise, normal operation continues. This parameter adaptation resolves the contradiction between frequent refresh and operation speed.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If refresh operations are performed frequently to maintain data integrity, then data retention is improved, but current consumption increases

Engineering Contradiction:
Improvedata integrityVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The refresh control circuit dynamically determines when refresh operations are needed by comparing current time with stored last access times. This dynamic approach ensures refresh operations are performed only when necessary to maintain data integrity, avoiding unnecessary energy consumption from frequent periodic refreshes while still preventing data loss when access patterns indicate risk.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The time table automatically tracks and updates last access times for each word line without external intervention. The refresh control circuit uses this self-maintained information to autonomously determine refresh timing, eliminating the need for external control logic and reducing overall system energy consumption while maintaining data integrity.

Inventive Principle:
Principle #25Self-service

3Reliability

If periodic refresh operations are implemented, then data loss is prevented, but operation time increases

Engineering Contradiction:
Improvedata retentionVSAvoidoperation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary tracking of access times by continuously updating the time table with last access time information for each word line. This preliminary action enables the refresh control circuit to predict when refresh operations will be needed and prepare accordingly, reducing the actual time penalty of refresh operations by avoiding last-minute urgent refreshes and allowing better timing coordination.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12431181B2Memory device and memory system with table to determine refresh timing
Publication Date: 2025.09.30 SK HYNIX INC
  • US12431181B2 patent drawing
  • US12431181B2 patent drawing
  • US12431181B2 patent drawing

AI summary

A memory device includes a memory cell array including a plurality of rows; a time table including a plurality of fields respectively corresponding to the rows; and a refresh control circuit configured to read field data from a k-th field of the time table according to an access command for a k-th row among the rows, where k is a natural number, determine whether to issue a refresh request signal for the k-th row based on current clock data and the field data, and update the field data of the k-th field using the current clock data.