Semiconductor Memory Refresh via Segmented Voltage Potentials
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Solution Overview
Problem
Conventional semiconductor memory device operations lead to high power consumption and inaccurate data state determination due to large voltage swings and charge pumping effects, which disturb unselected memory cells and reduce the net quantity of majority charge carriers in the electrically floating body region.
Innovation Solution
The method involves applying a series of voltage potentials to a semiconductor memory device, including a first voltage potential to a source line, a second to a local bit line, a third to a word line, and a fourth to a carrier injection line, with specific control signals to activate and deactivate transistors, manage voltage levels, and perform read and write operations, thereby reducing power consumption and maintaining accurate data state determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional reading and writing operations are performed with large voltage swings, then data state determination can be achieved, but power consumption increases and unselected memory cells are disturbed
Solution Approach 1:
The patent segments the memory device into selected and unselected memory cells, applying different voltage potentials to each group. The selected memory cell receives the full refresh voltage sequence while unselected memory cells receive reduced or zero voltage swings, thereby maintaining measurement precision for the selected cell while reducing overall power consumption and avoiding disturbance to unselected cells.
Solution Approach 2:
The patent applies local quality by providing different voltage potentials to different regions of the memory device. Specifically, the selected memory cell receives the complete refresh operation with appropriate voltage swings, while unselected memory cells receive minimized voltage potentials. This localized approach ensures accurate data state determination where needed while reducing power consumption across the entire device.
2Ease of manufacture
If pulsing between positive and negative gate biases is applied during read and write operations, then data writing can be achieved, but the net quantity of majority charge carriers in the electrically floating body region is reduced
Solution Approach 1:
The patent applies preliminary action by performing a refresh operation before normal read/write operations. The refresh operation restores the net quantity of majority charge carriers in the electrically floating body region by applying a sequence of voltage potentials that replenish charge carriers. This preliminary restoration ensures that subsequent data writing operations can proceed without excessive charge carrier depletion, maintaining both writing capability and charge carrier quantity.
Solution Approach 2:
The patent utilizes parameter changes by varying the voltage potentials applied to different terminals of the memory cell during the refresh sequence. By changing voltage parameters in a specific sequence (applying positive voltage to source line, then to bit line, then to gate), the patent restores charge carriers without causing the harmful charge pumping effect that occurs with conventional simultaneous pulsing of positive and negative gate biases.
3Reliability
If conventional writing techniques are used to increase majority charge carriers in the electrically floating body region, then data state can be set, but disturbance to unselected memory cells occurs
Solution Approach 1:
The patent segments the memory device into selected and unselected memory cells and applies different voltage potentials to each segment during write operations. The selected memory cell receives the full write voltage sequence to reliably set the data state, while unselected memory cells receive reduced or zero voltage swings. This segmentation ensures reliable data state storage in the selected cell without causing charge pumping or disturbance to unselected cells.
Solution Approach 2:
The patent applies local quality by providing enhanced voltage potentials and charge carrier injection specifically to the selected memory cell while maintaining minimal or zero voltage swings in unselected memory cells. This localized approach ensures reliable data state storage where needed while eliminating harmful disturbances to other memory cells in the array.
4Ease of operation
If charge pumping occurs during bias signal application, then transistor operation can be controlled, but the net quantity of majority charge carriers is reduced leading to inaccurate data state determination
Solution Approach 1:
The patent converts the harmful charge pumping effect into a beneficial refresh mechanism. By deliberately applying a sequence of voltage potentials that would normally cause charge pumping, the patent instead restores the net quantity of majority charge carriers in the electrically floating body region. The key difference is the timing and sequence: the refresh operation applies positive voltage to the source line first, then to the bit line, then to the gate, which replenishes charge carriers rather than depleting them. This transforms what would be a harmful effect into a useful charge restoration mechanism that improves data state determination accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, minimizes disturbance to unselected memory cells, and ensures accurate data state determination by maintaining constant voltage levels and optimizing voltage potentials during refresh operations, enhancing the overall performance of semiconductor memory devices.
Implementation Method 1
a third voltage potential to a word line of the array, wherein the word line is spaced apart from and capacitively to a body region of the memory cell that is electrically floating
Data Source
AI summary
Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for refreshing a semiconductor memory device may include applying a plurality of voltage potentials to a memory cell in an array of memory cells. Applying a plurality of voltage potentials to the memory cell may include applying a first voltage potential to a first region of the memory cell via a respective source line of the array. Applying a plurality of voltage potentials to the memory cells may also include applying a second voltage potential to a second region of the memory cell via a respective local bit line and a respective selection transistor of the array. Applying a plurality of voltage potentials to the memory cells may further include applying a third voltage potential to a respective word line of the array, wherein the word line may be spaced apart from and capacitively to a body region of the memory cell that may be electrically floating and disposed between the first region and the second region. Applying a plurality of voltage potentials to the memory cells may further include applying a fourth voltage potential to a third region of the memory cell via a respective carrier injection line of the array.