Semiconductor Memory Refresh Control for Weak Cell Retention
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Solution Overview
Problem
Semiconductor memory devices with defective memory cells are inefficiently discarded due to yield concerns, and existing refresh operations primarily focus on weak memory cells, neglecting the performance improvement of redundancy memory cells.
Innovation Solution
A semiconductor memory device design that includes a normal memory cell block, a redundancy memory cell block, weak cell information storage, and a refresh control circuit to manage the refresh rate of memory cells based on weak cell information, ensuring weak memory cells in both blocks are refreshed more frequently than others during a refresh cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh leveraging operation is applied only to weak memory cells among normal memory cells, then data retention of normal weak cells is improved, but redundancy memory cells remain under-optimized
Solution Approach 1:
The refresh control circuit is designed to universally apply refresh leveraging operations to both normal and redundancy memory cells. The circuit identifies weak cells in either block type and applies the same refresh strategy, making the system adaptable to different memory cell configurations while maintaining optimized data retention for all weak cells regardless of their block location.
2Device complexity
If all memory cells are refreshed at the same rate, then system operation is simple, but weak memory cells cannot be optimized
Solution Approach 1:
The refresh control circuit implements local quality by differentiating refresh operations based on memory cell characteristics. Weak memory cells (identified through training operations) receive enhanced refresh operations with additional refresh cycles, while strong cells use standard refresh. This localized optimization improves data retention for vulnerable cells without unnecessarily complicating the overall refresh control mechanism.
Solution Approach 2:
The system employs feedback through training operations that characterize each memory cell's strength. Based on this feedback, the refresh control circuit dynamically adjusts refresh strategies for individual cells or groups of cells. Weak cells identified through training receive more frequent or intensive refresh operations, creating a closed-loop system that optimizes reliability based on actual cell performance.
3Productivity
If redundancy memory cells are not optimized, then manufacturing yield is improved by having spare cells, but overall system performance is limited
Solution Approach 1:
The system performs preliminary training operations during manufacturing or initialization to identify weak memory cells in both normal and redundancy blocks before the device is put into service. This preliminary characterization allows the refresh control circuit to pre-configure optimized refresh strategies for redundancy cells, ensuring they are ready to serve as effective replacements if needed, thereby maximizing both yield and future reliability.
Data Source
AI summary
A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.