Memory Controller Region Channel Definitions

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Solution Overview

Problem

Multi-channel memory systems face challenges such as reduced bandwidth and increased power usage due to channel assignment inefficiencies, where masters with varying memory needs are allocated fixed, large channels, leading to idle resources and suboptimal memory density.

Innovation Solution

Implementing regional channel definitions within a memory system, where each region has its own channel configuration, allowing for customizable power usage and performance tuning by dividing memory cells into multiple regions with unique channel depths and definitions based on data type and usage patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If fixed, large channels are allocated to masters, then channel assignment is simplified, but bandwidth efficiency decreases and power usage increases due to idle resources

Engineering Contradiction:
Improvechannel assignment complexityVSAvoidbandwidth efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The memory system is divided into multiple regions, each with its own channel definition. This segmentation allows different masters to access different regions with appropriately sized channels, preventing the need for a single large channel that would remain partially idle. The patent implements this by creating region-specific channel definitions that match the actual memory access patterns of different masters.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different channel configurations are applied to different regions based on local requirements. General processors access general memory regions with standard channel definitions, while graphics processors access graphics memory regions with optimized channel definitions. This local quality approach ensures each region gets the appropriate channel size and configuration for its specific workload, improving overall bandwidth efficiency.

Inventive Principle:
Principle #3Local quality

2Device complexity

If fixed, large channels are allocated to masters, then channel assignment is simplified, but power consumption increases due to idle resources

Engineering Contradiction:
Improvechannel assignment complexityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by stationary object

Solution Approach 1:

By segmenting the memory system into regions with different channel definitions, the patent ensures that only the necessary channels are activated for each master's access pattern. This prevents power consumption associated with activating and maintaining idle channels that would occur with a fixed, large channel allocation scheme.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each region is configured with channel definitions matched to its specific access patterns, allowing the system to activate only the channels needed for current operations. This local optimization reduces overall power consumption by avoiding the activation of unnecessary channels that would be required by a uniform, oversized channel configuration.

Inventive Principle:
Principle #3Local quality

3Productivity

If memory cells are divided into multiple regions with unique channel definitions, then power usage and performance are optimized, but device complexity increases

Engineering Contradiction:
Improveperformance efficiencyVSAvoidmemory system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory controller is designed to handle multiple channel definitions universally, allowing it to manage different region configurations through a single unified interface. This multi-functionality approach maintains relatively low complexity by using one controller that can adapt to various region configurations rather than requiring separate controllers for each region type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system optimizes performance by changing parameters such as channel depth and definition based on the specific region being accessed. The memory controller dynamically adjusts these parameters according to the target region, allowing performance optimization without requiring fundamental changes to the overall system architecture or control logic.

Inventive Principle:
Principle #35Parameter changes

4Device complexity

If fixed channel assignments are used, then resource allocation is simplified, but memory density utilization decreases

Engineering Contradiction:
Improveresource allocation complexityVSAvoidmemory density utilization
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

Segmenting memory into regions with customized channel definitions allows the system to efficiently utilize memory density by matching channel capacity to actual access requirements in each region. This prevents the waste of memory capacity that occurs when fixed, oversized channels are used, as each region can be optimized for its specific workload characteristics.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By applying different channel definitions to different regions based on local access patterns, the system maximizes memory density utilization in each area. Graphics memory regions can be configured for high-capacity transfers while general memory regions use standard configurations, ensuring that total memory capacity is fully utilized without oversubscription in any single region.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3373150B1Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers
Publication Date: 2020.05.13 MICRON TECHNOLOGY INC
  • EP3373150B1 patent drawingFigure 1~2
  • EP3373150B1 patent drawingFigure 3~4
  • EP3373150B1 patent drawingFigure 5~7

AI summary

A method of accessing memory cells, wherein the cells are divided into at least a first region and a second region, the method comprising: accessing at least a first memory cell in the first region according to a first address definition, the first address definition including multiple bits identifying each of the bank, row, column, and channel depth for at least the first memory cell to be accessed in the first region, the first region having a first channel depth; and accessing at least a second memory cell in the second region according to a second address definition, the second address definition including multiple bits identifying each of the bank, row, column, and channel depth for at least the second memory cell to be accessed in the second region, the second region having a second channel depth different from the first channel depth of the first region.