Memory System Region Mapping for Read Write Latency
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Solution Overview
Problem
Multi-level cell-type non-volatile memory devices experience performance degradation due to longer read and write times compared to single-level cells, necessitating a method to enhance performance without compromising capacity.
Innovation Solution
A memory system with a non-volatile memory device and controller that categorizes logical clusters into normal, hot, and cold regions based on operation frequency, allowing for optimized access of Most Significant Bits (MSBs) and Least Significant Bits (LSBs, with the memory controller managing region mapping and data immigration to improve operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell is used to increase storage capacity, then storage capacity is improved, but read and write time increases causing performance degradation
Solution Approach 1:
The memory device is divided into multiple channels (first channel and second channel) that can operate independently and simultaneously. Each channel handles different data bits (MSB and LSB), allowing parallel processing of multi-level cell data to reduce overall access time while maintaining high storage capacity
Solution Approach 2:
The patent introduces a channel dimension to the memory architecture, transitioning from single-channel sequential access to multi-channel parallel access. This dimensional expansion allows simultaneous read/write operations on different data bits, effectively reducing access time while preserving multi-level cell capacity
2Quantity of substance
If multi-level cell is used to store more than one-bit data, then storage density is improved, but operation complexity increases
Solution Approach 1:
The multi-level cell data is segmented into separate bit components (MSB and LSB) that are accessed through different channels. This segmentation simplifies the read/write operations by allowing independent access to individual bits rather than requiring complex simultaneous manipulation of multiple bits
Solution Approach 2:
The patent introduces channel selection logic as an intermediary mechanism that directs read/write operations to appropriate channels based on the target data bit. This intermediary layer abstracts the complexity of multi-level cell operations, presenting a simplified interface to the controller while managing the underlying complexity of multi-bit storage
Data Source
AI summary
A memory system includes: a non-volatile memory device including a normal region in which Most Significant Bits (MSBs) and Least Significant Bits (LSBs) stored in memory cells are accessed simultaneously, a hot region in which MSBs stored in memory cells are accessed, and a cold region in which LSBs stored in memory cells are accessed; and a memory controller controlling the non-volatile memory device, Herein, the memory controller includes: a read/write counter that counts the number of read operations and the number of write operations that are performed for each of logical cluster to thereby produce a counting result; and a region selector that maps each logical cluster to one among the normal region, the hot region and the cold region based on the counting result to thereby produce mapping data.