Memory Region Programming for Fast Writes and Read Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in improving storage efficiency and reliability, particularly in managing data migration and program operations across different memory regions with varying states and conditions.
Innovation Solution
Implementing a memory device with distinct memory regions, each utilizing different program voltage increments and differences to optimize data writing and migration, ensuring threshold voltage convergence and increased read window margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is written to the first memory region using a large first difference between program voltages, then programming speed is improved, but threshold voltage distribution becomes wider reducing read reliability
Solution Approach 1:
The memory device is divided into a first memory region for fast programming and a second memory region for reliable storage. Data is first written to the first memory region with large voltage difference for speed, then migrated to the second memory region with small voltage difference for reliability. This segmentation resolves the contradiction by assigning different functions to different regions.
Solution Approach 2:
The first memory region acts as an intermediary buffer between the host and the second memory region. Data is temporarily stored in the first memory region with fast programming characteristics, then migrated to the second memory region for reliable long-term storage. This intermediary approach allows the system to benefit from both fast and reliable storage characteristics.
2Reliability
If data is migrated from the first memory region to the second memory region using a small second difference between program voltages, then read window margin is increased, but programming time is extended
Solution Approach 1:
Data is first quickly written to the first memory region as a preliminary action, achieving fast data ingress. Then, during idle periods or background operations, the data is migrated to the second memory region with smaller voltage differences to achieve better read window margins. This preliminary action approach separates the time-critical write operation from the quality-optimizing migration operation.
Solution Approach 2:
The migration from the first memory region to the second memory region is performed periodically or during idle states rather than continuously. This allows the system to maintain fast write performance while periodically optimizing the read window margin through migration operations, balancing speed and reliability requirements over time.
3Speed
If the memory device operates in an activated state, then data writing speed is improved, but power consumption increases
Solution Approach 1:
The memory device alternates between activated and idle states. During activated state, fast data writing is performed when needed. During idle state, migration operations are performed to maintain data reliability. This periodic switching allows the system to achieve fast write speeds when necessary while reducing power consumption during idle periods through low-power migration operations.
Data Source
AI summary
Examples of present disclosure disclose a memory device and an operation method thereof, and a readable storage medium. The memory device includes: a first memory region and a second memory region, each including a plurality of memory cells; and a peripheral circuit coupled with the first memory region and the second memory region and configured to: when writing data to the first memory region, perform a first program operation on memory cells to be programmed in the first memory region by using first program voltages that increase gradually; and when writing data in the first memory region to the second memory region, perform a second program operation on memory cells to be programmed in the second memory region by using second program voltages that increase gradually.