Nonvolatile Memory Region Switching for Write Speed and Lifespan
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Solution Overview
Problem
NAND flash memory devices face challenges in achieving high-speed writing while maintaining storage capacity and extending the lifespan of memory cells, particularly due to the need for repeated write operations and the differential wear between multi-bit and binary memory regions, leading to performance deterioration and reduced lifespan.
Innovation Solution
A nonvolatile semiconductor memory device design that dynamically switches data storage between regions based on rewriting frequency, where h-bit data is initially stored in one region and i-bit data in another, with region roles reversed or data stored in a new region when a prescribed rewriting threshold is reached, optimizing write operations and reducing wear.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is stored in all memory cells to increase storage capacity, then storage capacity is improved, but write speed deteriorates due to the need for repeated write operations
Solution Approach 1:
The memory cell array is divided into two distinct regions: a first region storing h-bit data and a second region storing i-bit data. This segmentation allows different write strategies to be applied to different regions, enabling high-speed writing in the first region while maintaining multi-bit storage capability in the second region, thus resolving the contradiction between storage capacity and write speed.
Solution Approach 2:
The patent implements dynamic region switching where the roles of first and second regions can be reversed when a prescribed rewriting count is reached. This dynamic adaptation allows the system to optimize write speed by frequently rewriting in the current first region while preserving less frequently accessed data in the second region, preventing the write speed deterioration that would occur with static multi-bit storage.
2Productivity
If memory cells are frequently rewritten to maintain high-speed writing, then write speed is improved, but memory cell lifespan deteriorates due to increased wear
Solution Approach 1:
By segmenting the memory into two regions with different rewrite frequencies, the patent allows the first region to be frequently rewritten (maintaining high write speed) while the second region is rewritten less frequently (preserving cell lifespan). The region switching mechanism ensures that no single region is overloaded with rewrites, thus resolving the contradiction between write speed and lifespan.
Solution Approach 2:
When a region reaches its prescribed rewriting count, the patent switches roles between regions, effectively discarding the heavily worn region from frequent write operations and recovering it for future use as the new second region. This allows the system to maintain high write speed in the active first region while preserving the overall lifespan of the memory device through periodic role reversal.
3Device complexity
If data is stored in a single region to simplify structure, then device complexity is reduced, but performance deteriorates due to uneven wear distribution
Solution Approach 1:
The patent maintains relatively simple structure by using only two regions instead of multiple complex wear-leveling zones. The dynamic switching between these two regions based on rewrite counts ensures uneven wear is balanced over time, preventing performance deterioration while keeping the structural complexity manageable. The switching logic is simple yet effective in distributing wear evenly across both regions.
Data Source
AI summary
A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦̸n) data is stored in a memory MLC of a first region MLB, and i-bit (i<h) data is stored in a memory SLC of a second region SLB. If the number of rewritings in the memory cells of the second region SLB reaches a prescribed value, the i-bit data is stored in the memory of the first region MLB rather than the memory cells of the second region SLB.