Memory Array and Register Reads Without Empty DQ Cycles
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Solution Overview
Problem
Memory devices experience performance degradation due to empty cycles on the DQ channel caused by the duration between receiving commands to access the memory array and registers, leading to latency and reduced system performance.
Innovation Solution
A memory device configured to receive consecutive commands for reading array data and register data during consecutive sets of clock cycles, allowing for simultaneous output of data without introducing empty cycles on the DQ channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device receives commands to access memory array and registers with a duration between them, then the device can properly process and output data, but empty cycles occur on the DQ channel reducing system performance
Solution Approach 1:
The memory device performs preliminary actions by receiving and processing the memory array read command first, then sequentially processing the register read command. The device prepares the data output path in advance and maintains continuous operation by eliminating idle cycles between commands, ensuring that the DQ channel remains actively transmitting data throughout the operation sequence.
Solution Approach 2:
The invention implements continuity of useful action by configuring the memory device to process commands in a continuous pipeline manner. The device receives the first command for reading array data, then immediately receives the second command for reading register data during overlapping time periods, ensuring that the data output operation continues without interruption or empty cycles on the DQ channel.
2Productivity
If the memory device outputs data from memory array and register during consecutive clock cycles, then empty cycles are eliminated, but the device complexity increases
Solution Approach 1:
The memory device segments the data output operation into distinct phases corresponding to different data sources. The device separately processes the first command for reading array data and the second command for reading register data, managing each command's data output independently through dedicated control logic that tracks command type and manages the respective data read and output operations.
Solution Approach 2:
The memory device implements multi-functionality by using a unified command reception and processing interface that handles both memory array read commands and register read commands through the same data output path. The device universally processes different command types by identifying the command source and routing the appropriate data through the shared DQ channel, eliminating the need for separate dedicated output circuits.
Data Source
AI summary
Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.