Memory Register Mode Switching for Multi-Frequency Testing
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Solution Overview
Problem
Existing memory systems face challenges with complex testing operations due to different clock frequencies and require larger space for testing circuits, which can be simplified to reduce complexity and size.
Innovation Solution
A simplified testing circuit for memory systems using a shift register with multiplexers to select inputs and clock frequencies, allowing operations at different frequencies while occupying less space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional testing circuits are used to support multiple clock frequencies, then testing capability is improved, but circuit complexity and space requirements increase
Solution Approach 1:
The register circuit is designed to perform multiple testing functions across different clock frequencies. The same register can operate at first clock frequency for initial testing and switch to second clock frequency for subsequent testing operations, eliminating the need for separate dedicated circuits for each frequency, thereby reducing overall circuit complexity while maintaining versatile testing capability
Solution Approach 2:
The register circuit dynamically switches between different operational modes corresponding to different clock frequencies. By enabling the register to adapt its operating frequency based on testing requirements, the circuit maintains flexibility and versatility without requiring static dedicated pathways for each frequency, thus reducing structural complexity
2Adaptability or versatility
If traditional testing circuits are used to support multiple clock frequencies, then testing capability is improved, but space requirements increase
Solution Approach 1:
A single register circuit serves multiple testing purposes across different clock frequencies, replacing what would traditionally require multiple separate testing circuits. This multi-functional approach significantly reduces the total space required while maintaining comprehensive testing capability for both first and second clock frequencies
Solution Approach 2:
The patent combines the functionality of multiple frequency-specific testing circuits into a single unified register structure. By merging these functions, the design achieves space efficiency while preserving the ability to perform testing operations at both first and second clock frequencies
3Area of stationary object
If simplified testing circuit is used, then space requirements are reduced, but testing operation complexity may increase
Solution Approach 1:
The register circuit is designed to automatically manage its own operational mode and clock frequency selection based on testing requirements. This self-service capability reduces operation complexity by eliminating the need for external control logic to manage frequency switching, as the register inherently adapts to the appropriate operating mode
Data Source
AI summary
Methods, systems, and devices for operational modes of a memory register are described. For example, a memory system may operate a register as a shift register, a multiple-input shift register (MISR) circuit, and a linear-feedback shift register (LFSR) circuit based on inputs provided to the register via respective multiplexers. In some instances, the register may operate as a shift register and a seed may be loaded to the associated flip-flops. The register may switch operational modes and may operate as a MISR circuit to test a data path between the associated memory system and a host system in the write direction. The register may also switch operational modes and may operate as a LFSR circuit to test the data path in the read direction. The register may operate in the respective modes based on inputs provided.