Memory Regulator Bias Circuit for Kickback Noise Cancellation
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Solution Overview
Problem
Memory devices experience significant kickback noise due to the configuration of regulators, which affects the performance and efficiency of memory components by introducing transient changes in the reference signal, leading to reduced voltage output and operational speed.
Innovation Solution
The regulator configuration is enhanced by positioning the enable circuit between the input circuit and the bias circuit, and optionally using a balance resistance or modifying the dimensions of the bias transistor to cancel bi-directional changes in voltage across parasitic capacitances, thereby reducing kickback noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the regulator is enabled for operation, then the memory device can function, but kickback noise is generated that affects performance
Solution Approach 1:
The patent converts the harmful kickback noise into a beneficial effect by intentionally generating an equal and opposite noise signal. The bias circuit is designed to produce kickback noise that cancels the noise from the enable circuit, transforming the harmful interference into a noise-cancellation mechanism that improves reference signal stability.
Solution Approach 2:
The patent applies the counterweight principle by creating a bias circuit that generates kickback noise as a counterbalancing force against the enable circuit's noise. The bias transistor and associated components are configured to produce an opposing voltage change that offsets the harmful kickback noise, effectively neutralizing its impact on the reference signal.
2Object-generated harmful factors
If additional filtering is added to reduce kickback noise, then noise is reduced, but device complexity increases
Solution Approach 1:
The patent implements self-service by designing the regulator's own internal bias circuit to generate the noise-cancellation signal. Instead of requiring external filtering components or additional noise-reduction circuitry, the system uses its inherent components (bias transistor, bias resistor, and capacitors) to automatically produce the counterbalancing kickback noise, eliminating the need for separate filtering mechanisms.
3Ease of operation
If the enable circuit is positioned traditionally, then the regulator operates, but transient voltage changes occur in the reference signal
Solution Approach 1:
The patent introduces the bias circuit as an intermediary element between the enable circuit and the reference signal. The bias circuit acts as a mediator that generates a compensating signal to offset the voltage transients caused by the enable circuit's operation, thereby stabilizing the reference signal without interfering with the enable function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively cancels the kickback noise, minimizing changes in the reference signal voltage and improving the performance and speed of memory components by matching the energy drawn and supplied by parasitic capacitances, thus reducing the need for additional filtering and maintaining voltage stability.
Implementation Method 1
an amount of energy drawn from the reference signal by the parasitic capacitance of one of the transistors (e.g., the input or bias transistor) may be canceled by an amount of energy supplied to the reference signal by the parasitic capacitance of the other of the transistors
Data Source
AI summary
Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.