Memory Regulator Layout for Kickback Noise Compensation
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Solution Overview
Problem
Memory devices experience significant kickback noise due to the configuration of regulators, which affects the performance and efficiency of memory components by introducing transient changes in the reference signal, leading to reduced voltage output and operational speed.
Innovation Solution
The regulator configuration is enhanced by positioning the enable circuit between the input circuit and the bias circuit, with optional balance resistance and modified transistor dimensions to reduce energy mismatch between parasitic capacitances, thereby canceling bi-directional voltage changes and minimizing kickback noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the regulator is enabled for operations, then the memory device can perform read/write operations, but kickback noise is generated that affects reference signal stability
Solution Approach 1:
An enable circuit is introduced as an intermediary component between the input circuit and bias circuit. This enable circuit acts as a mediator that controls the coupling between the two circuits, allowing the regulator to be enabled for operations while preventing direct kickback noise transmission to the reference signal input.
Solution Approach 2:
The regulator circuit is segmented into distinct functional blocks: input circuit, enable circuit, and bias circuit. By dividing the circuit into separable stages with the enable circuit positioned between input and bias circuits, the patent isolates the kickback noise generation site from the reference signal path, allowing operational functionality while reducing noise propagation.
2Object-affected harmful factors
If the enable circuit is positioned between the input circuit and bias circuit, then kickback noise is reduced, but the circuit configuration becomes more complex
Solution Approach 1:
The enable circuit is merged with the existing regulator structure, sharing common components such as transistors and capacitances with the input and bias circuits. This integration approach allows the enable functionality to be added without completely separate additional components, reducing the overall complexity increase while maintaining the noise reduction benefit.
3Object-affected harmful factors
If transistor dimensions are modified to balance parasitic capacitances, then energy mismatch is reduced and kickback noise is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent modifies transistor dimensions (width and length parameters) to adjust parasitic capacitance values. By changing these physical parameters of existing transistors rather than adding new components, the patent balances the energy exchange between input and bias circuits to minimize kickback noise, accepting tighter manufacturing tolerances as a trade-off for improved electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces kickback noise, ensuring a stable reference signal and improved performance by decoupling voltages across transistors, resulting in a more efficient energy supply to memory components.
Implementation Method 1
an amount of energy drawn from the reference signal by the parasitic capacitance of one of the transistors (e.g., the input or bias transistor) may be canceled by an amount of energy supplied to the reference signal by the parasitic capacitance of the other of the input and bias transistors
Data Source
AI summary
Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.