Memory Device Relative Error Count Access Control
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Solution Overview
Problem
Memory devices, especially those with on-die error correction logic, can accumulate errors that remain undetected by external hosts, making it difficult for users or manufacturers to predict device failure and assess the health of the fabrication process, as the baseline number of errors is inaccessible.
Innovation Solution
Implementing a mechanism within the memory device to track data errors locally and provide a relative error count to external agents, while restricting access to the baseline error count, allowing for improved memory management and failure prediction without compromising security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection logic is incorporated on-die with integrated memory circuit devices, then system reliability is improved through error correction, but access to error information is restricted making it difficult to predict device failure
Solution Approach 1:
The patent introduces an intermediary mechanism (error information interface and command processing logic) that mediates between the restricted on-die error detection logic and external hosts. This intermediary allows controlled access to error information through specific commands while maintaining security restrictions, enabling failure prediction without compromising the integrity of the error detection system.
Solution Approach 2:
The patent segments error information into different types (data errors, address errors, ECC errors) and provides selective access to different segments based on host privileges and command types. This segmentation allows useful error information to be accessed for reliability monitoring while keeping sensitive baseline error counts restricted.
2Measurement precision
If baseline error count is made accessible to external hosts, then device failure prediction capability is improved, but security is compromised exposing sensitive fabrication process information
Solution Approach 1:
The patent applies local quality by providing different levels of error information access to different hosts or access scenarios. Privileged hosts can access comprehensive error information including baseline counts for precise failure prediction, while standard hosts receive only relative error counts, maintaining security while enabling measurement precision where needed.
Solution Approach 2:
The patent changes the parameter of error information accessibility based on host privilege levels and command types. The system dynamically adjusts what error information is revealed by modifying response parameters according to the requesting host's authorization, allowing precise failure prediction for authorized users while maintaining security for unauthorized access attempts.
3Ease of operation
If comprehensive error information is provided to external agents, then memory management is improved, but device complexity increases due to access control mechanisms
Solution Approach 1:
The patent implements a universal command interface that handles multiple types of error information requests through a single standardized mechanism. The same command processing logic and interface structure handles both simple relative error count requests and complex baseline error count requests, reducing overall device complexity despite providing comprehensive error information access.
Data Source
AI summary
Techniques and mechanisms to provide selective access to data error information by a memory controller. In an embodiment, a memory device stores a first value representing a baseline number of data errors determined prior to operation of the memory device with the memory controller. Error detection logic of the memory device determines a current count of data errors, and calculates a second value representing a difference between the count of data errors and the baseline number of data errors. The memory device provides the second value to the memory controller, which is unable to identify that the second value is a relative error count. In another embodiment, the memory controller is restricted from retrieving the baseline number of data errors.