Hierarchical Memory Reliability Mapping for Dynamic Error Correction
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Solution Overview
Problem
Current memory systems lack a flexible method to set memory reliability levels tailored to different running objects, leading to inadequate memory reliability when various objects access memory under diverse conditions.
Innovation Solution
A memory access method and system that establishes hierarchical and flexible memory reliability levels by receiving reliability information from processors, mapping it to specific data and error correction code regions, and accessing data and error-tolerant codes accordingly, using predefined correspondence tables to ensure accurate data retrieval and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single error-tolerant coding method is used for memory, then the memory structure is simple and easy to manage, but it cannot meet the diverse reliability requirements of different running objects accessing memory under different conditions
Solution Approach 1:
The patent segments the memory access mechanism by dividing running objects into different types (first type and second type) and assigning different error-tolerant coding methods to each type. This segmentation allows the system to provide tailored reliability levels for different objects while maintaining clear management boundaries for each segment.
Solution Approach 2:
The patent implements a dynamic memory access mechanism where the error-tolerant coding method is selected based on the type of running object accessing the memory. The system dynamically adjusts the coding method (SEC-DED for first type, Chipkill for second type) according to the specific access request, enabling adaptability without requiring a completely static rigid structure.
2Reliability
If different error-tolerant coding methods are used for different running objects, then memory reliability requirements are met, but the memory access mechanism becomes complex
Solution Approach 1:
The patent introduces a memory management unit as an intermediary component that handles the complexity of selecting and managing different error-tolerant coding methods. This intermediary receives access requests, identifies the running object type, and automatically applies the appropriate coding method, thereby shielding the rest of the system from the complexity while ensuring high reliability.
Solution Approach 2:
The patent changes the parameter of error-tolerant coding method based on the running object type. By adjusting this parameter dynamically (SEC-DED vs. Chipkill), the system achieves different reliability levels without fundamentally changing the memory structure, thus managing complexity through parameter variation rather than structural complexity.
3Ease of operation
If error correction is performed only after error detection in SEC-DED method, then the coding method is simple, but it may not provide timely error correction for critical data access
Solution Approach 1:
The patent applies dynamic error correction timing based on the running object type. For second type objects with higher reliability requirements, the system performs error correction in advance before data access rather than only after detection. This dynamic timing adjustment ensures timely error correction for critical operations while maintaining simplicity for less critical accesses.
Solution Approach 2:
The patent implements preliminary error correction action for second type running objects by performing error correction before data access occurs. This preliminary action ensures that errors are corrected in advance for critical data, improving reliability and timeliness without affecting the simplicity of the basic SEC-DED approach for other objects.
Data Source
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AI summary
Embodiments of the present invention provide a memory access method, device, and system, so as to provide a hierarchical and flexible method for setting a memory reliability level to implement a memory access mechanism for different running object types and different reliability levels. The method provided in the embodiment of the present invention includes: receiving, by a memory device, reliability level information of a running object of a processor sent by the processor; establishing a first mapping relationship and a second mapping relationship according to the reliability level information of the running object; receiving an access request sent by the processor; and accessing data of the running object according to the access request and the first mapping relationship, and accessing error-tolerant code of the running object according to the access request and the second mapping relationship.