Semiconductor Memory Repair Address Latch and Plane Comparison
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Solution Overview
Problem
Flash memory apparatuses face inefficiencies in managing bad memory cells, as existing methods do not effectively utilize spare memory cells to replace disabled cells without wasting memory capacity, and there is a need for a systematic approach to activate memory cell groups based on repair addresses during initialization.
Innovation Solution
A semiconductor memory apparatus with a repair address latch unit, address comparison unit, and repair processing unit that compares input addresses with stored repair addresses and selectively activates corresponding memory cell groups in each plane, allowing for efficient allocation and use of spare memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spare memory cells are used to replace bad memory cells, then memory apparatus reliability is improved, but memory capacity is wasted
Solution Approach 1:
The memory device is divided into multiple planes (first plane, second plane), and repair addresses are segmented and stored in a repair address latch unit. The address comparison unit compares input addresses with stored repair addresses plane by plane, enabling selective activation of memory cell groups in specific planes without affecting other planes. This segmentation allows precise repair management and prevents unnecessary capacity waste.
2Reliability
If repair addresses are stored and compared for all planes, then bad memory cell management is improved, but device complexity increases
Solution Approach 1:
Repair addresses for multiple planes are pre-stored in the repair address latch unit during initialization. The address comparison unit performs preliminary comparison of input addresses with stored repair addresses before memory operations. This preliminary action enables quick identification of bad memory cells and appropriate repair routing without adding complex runtime processing.
Solution Approach 2:
The repair processing unit dynamically activates specific memory cell groups in specific planes based on comparison results. The activation is controlled by plane signals and start pulse signals that adaptively enable or disable memory cell groups according to the detected bad memory cells, providing flexible and dynamic repair management.
3Quantity of substance
If memory cell groups are selectively activated based on comparison results, then memory capacity utilization is improved, but processing time increases
Solution Approach 1:
The address comparison and memory cell group activation occur periodically during initialization and plane selection phases. The start pulse signal triggers periodic comparison cycles for each plane, allowing systematic processing of repair addresses without continuous overhead. This periodic action structure balances thorough repair management with efficient processing timing.
Data Source
AI summary
A semiconductor memory apparatus includes a memory device having a first plane and a second plane and a repair address latch unit configured to latch a plurality of repair addresses outputted from the memory device. The apparatus also includes an address comparison unit configured to compare the plurality of repair addresses stored in the repair address latch unit and a first plane address and a second plane address which are sequentially inputted. A repair processing unit is configured to selectively activate corresponding memory cell groups of the first plane and the second plane in conformity with the comparison result of the address comparison unit under the control of a first plane signal, a second plane signal and a start pulse signal.