Memory Repair Circuit Using Bitmap Address Mapping
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Solution Overview
Problem
Integrated circuit memory systems face inefficiencies in repairing defective locations, as existing methods often require specifying and communicating detailed defective memory addresses, which can be cumbersome and inefficient, especially during parallel testing of multiple circuits.
Innovation Solution
The implementation of multiple sets of memory cells, including a first set for regular data storage, a second set for substitution, and a third set for storing defective locations, along with control circuitry that responds to repair and test instructions to identify and replace defective cells without specifying their addresses, allowing for efficient data communication and parallel testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If defective memory addresses are specified and communicated in detail during repair operations, then the repair process can be precise, but the data communication burden increases and efficiency decreases
Solution Approach 1:
The patent extracts only the essential information needed for repair by using a bitmap format where each bit represents a memory location's defect status. Instead of transmitting complete address information for all defective cells, the system transmits a compact binary map that indicates only which locations need repair, significantly reducing communication overhead while maintaining repair precision.
Solution Approach 2:
The patent changes the representation parameter of defective locations from detailed address specifications to a compact bitmap format. This parameter transformation allows the system to convey defect information efficiently using minimal data bits, resolving the contradiction between precision and communication efficiency.
2Measurement precision
If detailed defective location information is communicated to each integrated circuit, then repair accuracy is maintained, but parallel testing efficiency is reduced
Solution Approach 1:
The patent creates a universal repair instruction format using the bitmap approach that can be applied across multiple integrated circuits simultaneously. The same compact bitmap instruction structure works for all circuits being tested in parallel, allowing the tester to send a single standardized instruction set that efficiently communicates defect information to multiple circuits without requiring circuit-specific detailed address lists.
Solution Approach 2:
The patent uses a standardized bitmap template that can be copied and applied to multiple integrated circuits. Instead of creating unique detailed defect lists for each circuit, the system uses the same compact bitmap representation format that can be efficiently transmitted to and interpreted by multiple circuits during parallel testing, thereby maintaining accuracy while improving productivity.
3Ease of repair
If multiple sets of memory cells are implemented for repair operations, then repair capability is enhanced, but device complexity increases
Solution Approach 1:
The patent segments the memory cell array into distinct functional regions: a first array for normal data storage, a second array for repair data storage, and a third array for defect location mapping. This segmentation allows each array to serve its specific purpose independently, enhancing repair capability while keeping the overall structure modular and manageable rather than monolithic and complex.
Solution Approach 2:
The patent introduces a third array that acts as an intermediary between the first array (normal memory) and the second array (repair memory). This intermediate defect location mapping array stores information about which cells need repair, serving as a mediator that coordinates the repair process without requiring direct complex interconnections between all memory arrays, thus reducing structural complexity while enhancing repair capability.
Data Source
AI summary
Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit.