Memory Repair Circuit Optimizing Redundant Address Allocation via ECC Virtual Repair
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory repair methods do not effectively account for error correction codes (ECC) when repairing fail memory cells, leading to inefficient use of redundant memory cells and potential errors.
Innovation Solution
A memory repair circuit and method that utilizes an ECC scheme to determine a repair order for memory packages based on fail information and redundant address counts, allowing for virtual repairs to identify addresses that can be corrected by ECC, thereby optimizing the use of redundant addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory repair methods are used without considering ECC, then all fail memory cells must be physically repaired using redundant cells, but this leads to inefficient use of redundant memory cells and potential errors when redundant cells are insufficient
Solution Approach 1:
The patent applies preliminary action by performing virtual repair operations before actual physical repair. The system first identifies fail bits through testing, then performs virtual repairs by logically marking fail addresses and checking if ECC can cover the remaining errors. This preliminary analysis determines which physical repairs are actually necessary, optimizing the use of redundant memory cells before committing to physical repair operations.
2Reliability
If all fail memory cells are repaired using redundant cells, then reliability is improved, but redundant memory cells may be insufficient leading to repair failures
Solution Approach 1:
The patent implements feedback by using ECC check results to guide the repair process. After virtual repair operations, the system checks whether ECC can cover the remaining fail bits. This feedback mechanism determines whether additional physical repairs are needed or if the current configuration is sufficient, preventing unnecessary consumption of redundant memory cells and avoiding repair failures due to insufficient redundancy.
3Productivity
If ECC is integrated into the repair process, then the need for physical repairs is reduced, but the complexity of the repair circuit increases
Solution Approach 1:
The patent applies merging by integrating ECC functionality with the repair circuit operations. The ECC encoder and decoder are combined with the virtual repair logic, allowing the system to perform error correction and repair decision-making in a unified process. This integration enables the repair circuit to leverage ECC capabilities without requiring completely separate processing paths, balancing functionality with circuit complexity.
Data Source
AI summary
A memory repair circuit of a memory module including a plurality of memory packages, the memory repair circuit including: a test circuit configured to test the plurality of memory packages to obtain fail information in each of the plurality of memory packages; and a redundancy analysis circuit configured to: obtain a redundant address count in each of the plurality of memory packages, determine a repair order of the plurality of memory packages based on the fail information and the redundant address count, and perform a virtual repair on the plurality of memory packages in the repair order to determine an address to be repaired in each of the plurality of memory packages.