Memory Repair Circuit Using Fail Bit Table for Defective Cell Replacement
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Solution Overview
Problem
The increasing number of defective cells in memory devices due to their miniaturization and high integration poses challenges in achieving high-capacity compact memory devices, as it reduces production yield and requires additional spare cells for repair.
Innovation Solution
A memory device with a repair circuit that uses a fail bit location information table to store and compare row and column address information of defective cells, enabling efficient replacement with spare cells in a separate area, minimizing the number of additional spare cells needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are miniaturized and highly integrated to increase capacity, then memory capacity and integration are improved, but the number of defective cells increases and production yield deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-storing the address information of defective cells in a fail bit location information table before normal operation. When a defective cell is accessed, the repair circuit can immediately retrieve its address from the pre-stored information and redirect the access to a spare cell, enabling rapid repair without adding significant overhead to the access time.
Solution Approach 2:
The patent introduces an intermediary repair circuit that acts as a mediator between the memory cell array and the external interface. This repair circuit includes a row address comparison unit and a column address comparison unit that intercept address signals, compare them against stored defective cell addresses, and redirect accesses to spare cells when defects are detected, thereby shielding the external system from the presence of defective cells.
2Reliability
If additional spare cells are added to repair defective cells, then defective cell repair capability is improved, but device complexity and area increase
Solution Approach 1:
The patent applies segmentation by dividing the repair function into distinct modular components: a fail bit location information table for storing defective cell addresses, a row address comparison unit for comparing row addresses, and a column address comparison unit for comparing column addresses. This modular segmentation allows each component to perform its function independently, simplifying the overall design and making the repair circuit easier to implement and maintain.
Solution Approach 2:
The patent applies universality by designing a repair circuit that can handle multiple defective cells using a unified approach. The fail bit location information table can store addresses of multiple defective cells, and the comparison units can identify and repair any defective cell within the memory array, making the repair mechanism universally applicable to various defect locations without requiring separate repair circuits for each defective cell.
3Reliability
If additional spare cells are added to repair defective cells, then defective cell repair capability is improved, but device area increases
Solution Approach 1:
The patent applies local quality by implementing repair functionality only at the specific locations where defective cells are identified and stored in the fail bit location information table. Rather than providing universal repair coverage across the entire memory array, the repair circuit focuses its resources on the specific defective cell addresses that have been pre-identified and stored, thereby minimizing the area required for spare cells and repair circuitry while still achieving effective repair of known defects.
Data Source
AI summary
A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array. The repair circuit also includes a row address comparison unit configured to compare the row address of the defective cell with a row address of a first access cell received from the outside, and to output a first row match signal when the defective cell's row address matches the row address of the first access cell, and a column address comparison unit configured to compare the column address of the defective cell with a column address of the first access cell received from the outside, and to output a first column address replacement signal if the column address of the defective cell is the same as the column address of the first access cell.