Memory Repair Circuit for External Test-Result Output
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, face challenges in reliability and productivity due to defects that are not detected during initial testing, leading to increased costs and reduced efficiency, especially when low-performance test equipment is used for package testing without built-in self-test circuits.
Innovation Solution
A memory device with a repair circuit that utilizes redundancy memory cells to repair failed memory cells, outputting signals to external destinations indicating repair status and capacity, enabling efficient post-package repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If low-performance test equipment is used for package testing, then cost is reduced, but measurement precision and reliability of defect detection deteriorate
Solution Approach 1:
The patent applies preliminary action by performing an initial EDS test during manufacturing using high-performance test equipment to identify and repair defective memory cells before packaging. This preliminary defect detection and repair ensures that only properly functioning memory cells are packaged, allowing subsequent package testing to use lower-cost, low-performance test equipment while maintaining overall product reliability.
2Reliability
If BIST circuit is included in DRAM, then reliability and defect detection capability are improved, but device complexity and physical area occupied increase
Solution Approach 1:
The patent extracts the BIST functionality from the DRAM chip itself and relocates it to an external host system. Instead of including complex TPG circuits and BISR circuits within the DRAM device, the patent implements test pattern generation and defect analysis in the host computer, thereby reducing the DRAM's internal complexity and physical area requirements while maintaining defect detection and repair capabilities.
3Productivity
If redundant memory cells are used for repair operations, then productivity and yield are improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-identifying defective memory cells through EDS testing and pre-assigning redundant memory cells to replace them before packaging. The repair circuit stores the correspondence relationships between defective addresses and redundant addresses in advance, enabling efficient repair operations without requiring complex real-time defect analysis circuits during normal operation.
Data Source
AI summary
A memory device includes a memory cell array and a repair circuit configured to perform a repair operation and output a dirty signal to an external destination external to the memory device. The repair circuit further performs selecting a first redundancy address of the redundancy memory cells instead of a first fail address of the first failed memory cell, storing a first redundancy mapping for the first fail address to the first redundancy address, and in response to determining a second fail address of a second failed memory cell matches the first fail address, ignoring the first redundancy mapping, and outputting a dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.