Circuit Simulation for Memory Repair Verification
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently verifying and repairing memory cell failures, particularly in large memory arrays where dedicated repair verification is time-consuming due to the numerous redundant memory cells.
Innovation Solution
A method of circuit simulation that initializes a simulation environment by selecting a subset of memory cells (N between 10 and 20) for repair verification, simulating the circuit, and outputting a result file including repair verification results, allowing for gradual completion of repair verification during other simulation processes, thereby improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated repair verification is performed on all memory cells in large memory arrays, then repair verification completeness is improved, but time consumption increases significantly
Solution Approach 1:
The patent divides the memory array into multiple banks, with each bank containing a subset of memory cells. Instead of verifying all cells in the entire array, the verification process is segmented to operate on individual banks independently. This segmentation allows parallel processing of multiple banks and significantly reduces the time required for complete repair verification while maintaining verification completeness across the entire memory array.
2Measurement precision
If repair verification is performed on a large number of memory cells, then verification accuracy is improved, but processing efficiency deteriorates
Solution Approach 1:
The patent implements a two-stage verification approach: first performing a quick verification on a subset of memory cells (partial action) to identify obviously defective cells, and then performing comprehensive verification only on cells that require further inspection. This partial action strategy maintains high verification accuracy for critical cells while improving overall processing efficiency by avoiding exhaustive verification of all cells.
Solution Approach 2:
The patent performs preliminary verification steps before complete repair verification. This includes initial detection of memory cell status, preliminary assessment of repair needs, and pre-processing of verification data. These preliminary actions prepare the system for more efficient subsequent verification processes, reducing the time and computational resources required for complete verification while maintaining accuracy.
Data Source
AI summary
The present disclosure provides a method of circuit simulation, a test apparatus, an electronic device, and a medium. The method includes: initializing a simulation environment, including selecting N memory cells from a memory array as to-be-verified cells, and performing repair verification on each to-be-verified cell; simulating the circuit, where the circuit includes an array region circuit and a peripheral region circuit; and outputting a circuit simulation result file, the circuit simulation result file including a result of repair verification for each to-be-verified cell.