Memory Repair Circuit Testing via Address Match and Enable Path Check
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Solution Overview
Problem
Faulty repair circuits in semiconductor memory devices, such as DRAM, lead to reduced yield and reliability due to unstable or impossible repair operations, as defects in the repair circuit itself are not detected during testing.
Innovation Solution
A method is introduced to test the repair circuit by storing first and second addresses in registers, comparing bit values, and generating repair enable signals based on hit signals to determine the status of the repair circuit's operation, ensuring stable repair operations can be verified.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the repair circuit is used to replace faulty memory cells, then the functionality of defective memory cells is restored, but the reliability of the memory device may be compromised if the repair circuit itself is faulty
Solution Approach 1:
The patent applies preliminary action by testing the repair circuit before final product formation. The test method verifies the repair circuit's functionality in advance by providing test addresses, comparing them with stored faulty addresses, and checking the generated repair enable signals. This preliminary verification ensures the repair circuit is functional before the memory device is committed to production, preventing reliability issues from manifesting later.
Solution Approach 2:
The repair circuit performs self-verification through the test method. By incorporating the repair circuit into the testing process itself, the system enables the repair circuit to demonstrate its own functionality. The test addresses are compared against stored faulty addresses, and the repair enable signals are monitored to confirm the circuit operates correctly, allowing the system to self-validate without external intervention.
2Productivity
If the repair circuit operation is verified through testing, then the yield and reliability of memory devices are improved, but additional testing time and complexity are required
Solution Approach 1:
The patent merges the repair circuit testing function with the existing test operation infrastructure. The test method utilizes the same test addresses, comparison logic, and signal generation pathways that are already part of the memory device's operational test sequence. By integrating the repair circuit verification into the existing test framework rather than creating a separate testing process, the patent minimizes additional testing time while improving yield.
Solution Approach 2:
The test method demonstrates multi-functionality by using a single testing sequence that simultaneously verifies both the memory cell array functionality and the repair circuit operation. The test addresses serve dual purposes: they test normal memory operations and also trigger the repair circuit's address comparison and signal generation functions. This universal approach allows one test sequence to accomplish multiple verification goals, reducing overall testing time.
Data Source
AI summary
A method of testing a repair circuit of a memory device. The method may include storing first addresses in a first register of the repair circuit, wherein the first register is configured to store faulty addresses during a normal operation of the memory device, and the repair circuit is configured to perform a repair operation to replace the faulty addresses with redundancy addresses, storing test addresses in a second register of the repair circuit, wherein the test addresses are provided from a test host, outputting hit signals by comparing bit values of the addresses stored in the first register with bit values of the addresses stored in the second register, outputting repair enable signals based on the hit signals, and determining a status of a path where the repair enable signals are generated based on logic levels of the repair enable signals.