Memory Repair Control Circuit Dynamic Granularity
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Solution Overview
Problem
As DRAM miniaturization progresses, the occurrence rate of memory cell defects increases, necessitating effective repair methods to maintain memory capacity, as existing techniques struggle to efficiently vary repair units and adapt to different failure types.
Innovation Solution
A memory device with a repair control circuit that compares input addresses with stored failed addresses, activating redundancy word or bit lines to dynamically adjust the repair unit based on address bits, allowing for flexible repair operations using redundancy resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If miniaturization is pursued to increase memory capacity, then memory density is improved, but the occurrence rate of memory cell defects increases
Solution Approach 1:
The patent performs preliminary detection of defective cells during manufacturing and stores their addresses in non-volatile memory. Repair mappings are pre-configured to map defective cells to spare cells, so that when defects occur due to miniaturization, the repair mechanism is already in place and can be activated without adding extra redundancy cells, thus maintaining memory capacity while compensating for increased defect rates
Solution Approach 2:
The patent changes the parameter of repair granularity by supporting both row-level and column-level repair operations. The repair control circuit can dynamically select the appropriate repair unit size based on the defect pattern, allowing efficient use of limited spare cells while maintaining reliability despite higher defect occurrence from miniaturization
2Device complexity
If fixed repair units are used, then repair control is simplified, but adaptability to different failure types is reduced
Solution Approach 1:
The patent implements dynamic repair unit selection where the repair control circuit can switch between row repair and column repair modes based on the defect pattern. The system determines whether to perform row-level or column-level repair by analyzing the address of defective cells, allowing the repair granularity to adapt to different failure types while maintaining reasonable control complexity through automated decision-making
Solution Approach 2:
The patent creates a universal repair mechanism that can handle multiple types of defects (row defects, column defects, isolated cell defects) using the same spare cells. The repair control circuit universally applies address comparison and mapping techniques regardless of defect type, making the system adaptable to various failure modes without requiring separate repair mechanisms for each case
Data Source
AI summary
A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.