Semiconductor Memory Repair Controller SPPR Refresh Logic
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Solution Overview
Problem
In semiconductor memory devices, the refresh operation in soft post-package repair (SPPR) mode faces challenges as memory blocks share a common enable signal, leading to improper refresh operations for non-target memory blocks, especially when trying to access either the normal or redundant cell regions simultaneously.
Innovation Solution
A semiconductor memory device with a repair controller that generates a mode enable signal for accessing the SPPR region by comparing repair address information with the row address, and disables this signal during a refresh command, ensuring proper selection and refresh of memory cell arrays without overlap between normal and redundant cell regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory blocks share a common enable signal for parallel refresh operations, then refresh operation speed is improved, but improper refresh operations occur for non-target memory blocks
Solution Approach 1:
The patent segments the common enable signal into individual block-specific enable signals (e.g., first block selection signal, second block selection signal) for each memory block. This segmentation allows each memory block to be independently controlled during refresh operations, ensuring that only the target memory block is refreshed while others remain inactive, thus resolving the conflict between parallel refresh speed and operational accuracy.
Solution Approach 2:
The patent implements dynamic control of block selection signals based on the refresh command and target address. The enable signals are dynamically activated only for the specific memory block being refreshed, while other blocks remain disabled. This dynamic approach maintains the efficiency of parallel operations while ensuring precision in selecting the correct target block.
2Productivity
If block selection signals are enabled concurrently for parallel refresh, then productivity is improved, but data loss occurs due to overlapping refresh operations
Solution Approach 1:
The patent divides the refresh operation into separate, non-overlapping segments for each memory block by using individual block selection signals. Each signal enables only its corresponding memory block during the refresh operation, preventing the overlapping that causes data loss while maintaining high throughput through coordinated parallel execution of segmented operations.
Solution Approach 2:
The patent applies preliminary anti-action by disabling block selection signals for non-target memory blocks before the refresh operation begins. This preventive measure ensures that no overlapping refresh operations can occur, protecting data integrity in advance while allowing the target block to be refreshed efficiently.
3Device complexity
If SPPR mode uses a shared enable signal, then device complexity is reduced, but measurement precision of target address selection deteriorates
Solution Approach 1:
The patent segments the control signal structure by providing separate block selection signals for each memory block instead of using a single shared enable signal. This segmentation improves target address selection accuracy by precisely identifying which block to refresh, while the overall control structure remains relatively simple through systematic signal distribution.
Solution Approach 2:
The patent maintains a universal control approach where the same block selection signal mechanism serves multiple functions: it enables parallel refresh operations, prevents overlapping operations, and ensures accurate target block selection. This multi-functionality achieves high precision without significantly increasing device complexity.
Data Source
AI summary
A semiconductor memory device includes: a plurality of memory cell arrays each memory cell array including a first region, a second region, and a third region in the second region; and a repair controller suitable for storing a first repair address information, generating a first mode enable signal for accessing the third region by comparing the first repair address information with a row address during a first mode for a repair operation, and disabling the first mode enable signal in response to a refresh command regardless of a result of the comparing the first repair address information with the row address.