Memory Repair System With Daisy Chain BISR
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Solution Overview
Problem
Existing memory repair systems for integrated circuits are limited in their ability to accommodate a mixture of parallel and serial repair approaches and are specific to the number, size, and configuration of embedded memory locations, leading to inefficiencies in resource usage and increased information overload during testing phases.
Innovation Solution
A serially clocked, closed-loop daisy chain memory repair system with a central fuse box, fuse box interface, and BISR registers that stores memory repair data in a high-order compression scheme, allowing for flexible integration of non-volatile memories and accommodating various memory configurations, enabling efficient data transfer and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a centralized fuse box stores memory repair data for multiple embedded memories, then resource usage is minimized and manufacturing cost is reduced, but information overload occurs during testing phases and device complexity increases
Solution Approach 1:
The system segments the centralized fuse box into multiple distributed repair memory structures, with each embedded memory having its own dedicated repair memory. This segmentation distributes the storage burden and eliminates information overload during testing, as each memory can be tested and repaired independently without interference from other memories.
Solution Approach 2:
The patent introduces a hierarchical dimension to the repair system by implementing both individual repair memories for each embedded memory and a centralized fuse box. This multi-level structure allows the system to benefit from both distributed simplicity (for testing) and centralized resource efficiency (for storage), effectively resolving the contradiction between resource usage and device complexity.
2Ease of manufacture
If repair data is stored in a centralized fuse box, then manufacturing cost is reduced, but off-chip testing becomes more complex and time-consuming
Solution Approach 1:
The system performs preliminary repair data storage in distributed repair memories during manufacturing, allowing each embedded memory to be pre-configured with its own repair data. This preliminary action eliminates the need for complex off-chip testing of centralized fuse box data, significantly reducing testing time while maintaining manufacturing cost benefits.
3Productivity
If individual repair memories are provided for each embedded memory, then testing is simplified and speeded up, but resource usage increases and manufacturing cost rises
Solution Approach 1:
The patent merges the benefits of distributed repair memories with a centralized fuse box by implementing a hierarchical structure where individual repair memories handle fast local testing and repair, while the centralized fuse box provides efficient long-term storage. This combination achieves both fast testing speed and resource efficiency by allowing repair data to be temporarily stored locally during testing and then consolidated to the centralized storage.
Data Source
AI summary
A system for repairing embedded memories on an integrated circuit includes an external Built-In Self-repair Register (BISR) associated with every reparable memory. Each BISR is serially configured in a daisy chain with a fuse box controller. The controller determines the daisy chain length upon power up. The controller may perform a corresponding number of shift operations to move repair data between BISRs and a fuse box. Memories can have a parallel or serial repair interface. The BISRs may have a repair analysis facility into which fuse data may be dumped and uploaded to the fuse box or downloaded to repair the memory. Pre-designed circuit blocks provide daisy chain inputs and access ports to effect the system or to bypass the circuit block.