Semiconductor Memory Repair via Data Copy
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Solution Overview
Problem
Existing semiconductor repair methods often result in data loss from normal memory cells during the replacement of defective memory elements, as they replace entire row or column lines, even if only a small number of memory cells are defective.
Innovation Solution
A semiconductor apparatus and memory system that performs a data copy operation from normal memory cells to redundant memory cells and writes the fail address to a fuse cell array, allowing for targeted repair without data loss, using a fuse cell array, address generation circuit, control circuit, and command generation circuit to manage the data copy and repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire row or column lines are replaced during repair operation, then the defective memory elements can be replaced with redundant elements, but data stored in normal memory cells will be lost
Solution Approach 1:
The repair operation is segmented into two distinct phases: first, data copy operation that selectively copies data from normal memory cells to redundant memory cells based on defect location; second, repair operation that replaces defective elements. This segmentation allows precise targeting of only defective elements rather than replacing entire row or column lines, thereby preventing data loss from normal memory cells.
Solution Approach 2:
The data copy operation is performed as a preliminary action before the actual repair operation. By copying data from normal memory cells to redundant memory cells in advance, the system ensures data preservation before the repair process begins. This preliminary data preservation step enables subsequent replacement of defective elements without risk of data loss.
2Loss of information
If targeted repair of only defective memory cells is performed, then data from normal memory cells is preserved, but additional operations are required before repair
Solution Approach 1:
The memory apparatus is designed with multi-functionality to handle both data copy operations and repair operations through a unified control circuit. The control circuit can selectively execute different operation modes (data copy or direct repair) based on defect characteristics, making the additional data copy operation unnecessary for cases where direct repair is safe, thereby reducing overall system complexity while preserving data when needed.
Data Source
AI summary
A semiconductor apparatus may include a fuse cell array, an address generation circuit, a control circuit, and a command generation circuit. The fuse cell array may store a fail address. The address generation circuit may generate a copy address according to test information containing the fail address. The control circuit may control a repair operation including enabling a copy start signal according to the test information and storing the fail address in the fuse cell array according to a copy done signal. The command generation circuit may generate an address and a plurality of commands for a data copy operation according to the copy start signal and enable the copy done signal when the data copy operation is completed.