Memory Repair Circuit for In-Market Defect Recovery
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Solution Overview
Problem
Existing semiconductor memories with reduced chip area face increased defect rates in the market due to small voltage margins, necessitating effective memory repair solutions.
Innovation Solution
A memory repair circuit and method that generates and stores repair codes based on test results, both during mass production and in the market, using a fuse circuit and a field test control circuit to reconfigure memory access and alleviate defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chip area is reduced to improve integration, then manufacturing cost decreases, but defect rate increases due to small voltage margins
Solution Approach 1:
The patent performs memory repair operations in advance during mass production testing before the memory devices are shipped to customers. Test patterns are applied to detect defective memory cells, and repair codes are generated and stored in fuse circuits or non-volatile memory during this preliminary phase. This preliminary action ensures that defective cells are identified and compensated for before the devices enter the market, thereby improving reliability without requiring larger chip area.
2Reliability
If memory repair is performed in the market, then reliability improves, but test time increases
Solution Approach 1:
The patent performs memory repair operations during mass production testing before shipping, rather than waiting for market deployment. Test patterns are applied to detect defective cells, repair codes are generated, and fuse circuits are programmed during this preliminary manufacturing phase. This eliminates the need for extended testing in the market, thereby improving reliability without significantly increasing the time loss in the field.
Solution Approach 2:
The memory device performs self-diagnosis and self-repair through built-in test circuits and fuse circuits that are integrated within the device itself. The repair control circuit automatically generates repair codes and reconfigures memory access patterns without requiring external intervention or manual repair processes. This self-service capability streamlines the repair process and reduces the time required for memory reliability improvement.
3Reliability
If external intervention is required for memory repair, then repair accuracy improves, but device complexity increases
Solution Approach 1:
The memory device incorporates built-in test circuits, repair control circuits, and fuse circuits that enable autonomous self-diagnosis and self-repair operations. Test patterns are applied internally, defective cells are detected automatically, repair codes are generated by the repair control circuit, and fuse circuits are programmed without external intervention. This self-service approach maintains high repair accuracy while minimizing the increase in device complexity, as all repair functions are integrated within the memory device itself.
Data Source
AI summary
Provided is a memory repair circuit including a memory built-in self-test (MBIST) circuit that generates a repair code on the basis of a test result in a market, a register that holds the generated repair code, and a path for transmitting the repair code to a repair circuit. The memory repair circuit may include a logical circuit that performs a logical operation of a repair code generated at the time of mass production and a repair code based on the test result in the market.