Memory Repair Circuit for Boundary Fault ECC Bypass
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Solution Overview
Problem
Global redundant column select (GRCS) implementations in memory devices face delays in error correction code (ECC) processing due to data multiplexing and are constrained by ECC specifications, which can limit the safe usage of certain implementations, particularly in cases of boundary faults where multiple data lines on a sub-word line exceed permissible corrections.
Innovation Solution
The implementation of repair circuitry that uses a global column plane to bypass faulty column planes by transmitting outputs to both a multiplexer and a logic gate, allowing for concurrent or parallel processing with error correction circuitry, and setting default values for repaired column planes to avoid bit error evaluations, thus enabling faster ECC computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data multiplexing is used in GRCS implementation, then redundant memory elements can be activated to correct errors, but ECC processing is delayed
Solution Approach 1:
The patent segments the data path by creating separate routes: one path for normal data flow and another path for repaired data from the global column plane. This segmentation allows ECC processing to occur on normal data without waiting for multiplexing operations, thereby reducing ECC processing delay while maintaining error correction capability through the alternative repair path.
Solution Approach 2:
The patent performs repair operations in advance by pre-processing data through the global column plane before it reaches the multiplexer stage. This preliminary action allows the repaired data to be ready concurrently with normal data flow, eliminating the need for ECC to wait for multiplexing completion and thus reducing processing delay.
2Reliability
If GRCS implementation is used to repair boundary faults, then more data lines can be corrected, but ECC specification limits are exceeded
Solution Approach 1:
The patent applies local quality by selectively enabling the global column plane repair path only for specific boundary fault conditions that meet ECC specification criteria. The system evaluates whether a fault qualifies for GRCS repair based on its location and characteristics, applying the repair mechanism locally to qualifying cases while maintaining standard processing for others, thus ensuring ECC specification compliance.
Solution Approach 2:
The patent introduces an intermediary evaluation mechanism that assesses whether a detected fault qualifies for GRCS repair before activating the repair path. This intermediary layer ensures that only faults meeting ECC specification requirements (such as boundary fault conditions) are repaired through the global column plane, preventing specification violations while maintaining correction capability for eligible cases.
3Reliability
If multiple DQs are used for boundary faults, then more errors can be corrected, but the number of DQs on SWL exceeds the limit
Solution Approach 1:
The patent resolves the DQ allocation problem by transitioning from a two-dimensional allocation (within a single SWL) to a three-dimensional solution that utilizes the global column plane as an additional dimension. This allows the system to access more data lines for correction purposes without increasing the number of DQs allocated to any single SWL, thereby maintaining compliance with device complexity constraints while expanding error correction capacity.
Data Source
AI summary
An electronic device includes memory banks and repair circuitry configured to remap data from the memory banks to repair memory elements of the memory banks when a failure occurs. The repair circuitry includes a logic gate configured to receive an output from a memory bank of the memory banks, receive a failure signal indicating whether a corresponding memory element has failed, and transmit the output with a value of the output is based at least in part on the failure signal. The repair circuitry also includes error correction circuitry configured to receive the output via the logic gate and a multiplexer configured to receive the output from the memory bank, receive a repair value, and selectively output the output or the repair value from the repair circuitry as an output of the repair circuitry.