Memory Repair Using External Tags for Defective Cell Replacement
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Solution Overview
Problem
Dynamic memory devices face issues with weak memory cells that do not retain data for a specified minimum time, requiring a solution to replace their storage function effectively without affecting overall memory performance.
Innovation Solution
The implementation of a memory system where defective cells are replaced by 'repair cells' arranged in an extra column of memory array tiles, with a tag memory storing addresses of defective cells in a content-addressable manner to direct data retrieval or storage to these repair cells on a cell-by-cell basis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If defective memory cells are replaced by repair cells, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory array is segmented into functional blocks with dedicated repair cells for each block. Each repair cell corresponds to specific defective cells, allowing localized repair without affecting the entire memory array. This segmentation enables targeted replacement of defective cells while maintaining the overall structure.
Solution Approach 2:
Multiplexer circuits serve as intermediaries between the main memory array and repair cells. These multiplexers selectively connect defective cells to their corresponding repair cells based on defect location, enabling dynamic routing of read/write operations without permanent structural changes to the memory array.
2Reliability
If repair cells are integrated into the memory array, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Repair cells are designed with local quality characteristics specific to their repair function. Each repair cell is optimized for its particular repair role, with dedicated circuitry and connectivity patterns that differ from standard memory cells. This allows repair cells to be manufactured with slightly different specifications without affecting the overall manufacturing process.
Solution Approach 2:
Repair cells are organized in a separate dimensional structure from the main memory array, accessed through additional address lines and control signals. This dimensional separation allows repair cells to be manufactured and tested independently before integration, reducing the precision requirements for their placement within the overall memory device.
3Reliability
If cell-by-cell repair is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
Defective cells are identified and mapped to repair cells during the manufacturing testing phase, before the device is shipped to the customer. This preliminary identification allows the repair mapping information to be stored in non-volatile memory, so that the complex repair control logic is pre-configured and does not need to be dynamically determined during operation.
Solution Approach 2:
The repair mapping information is copied from manufacturing test data into a lookup table stored in the memory device. This copying process transfers the complex repair configuration data into a format that can be efficiently queried during normal operation, reducing the real-time computational complexity of the repair control circuitry.
4Productivity
If repair operations are performed during normal operation, then productivity is maintained, but reliability may be affected
Solution Approach 1:
The memory system performs periodic self-diagnostics to detect defective cells during normal operation. When defects are detected, the system periodically switches between using main memory cells and their corresponding repair cells, allowing repair operations to be integrated into the normal operational cycle without requiring continuous disruption.
Solution Approach 2:
The memory device includes error detection and correction circuits that provide a buffer against repair operation failures. These circuits can detect issues during repair operations and switch to alternative repair cells or error correction mechanisms, cushioning against potential reliability problems that might arise during dynamic repair operations.
Data Source
AI summary
A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.