Memory Cell Repair via Fail Address Storage and Anti-Fuse Array
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Solution Overview
Problem
As semiconductor chip manufacturing becomes more refined, with smaller and more tightly integrated features, errors during the manufacturing process and operation of dynamic random access memory (DRAM) and other memory devices become more likely, necessitating effective methods for detecting and repairing defective memory cells.
Innovation Solution
A test device and method that includes an error correcting code (ECC) engine and built-in-self-test (BIST) circuit to determine fail addresses in memory cells, temporarily store them in a fail address memory, and transmit them to a non-volatile storage array for storage and repair, using a system-on-chip (SOC) configuration with a CPU and memory controller to control the repair process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor manufacturing process is refined with smaller and more tightly integrated features, then manufacturing precision and integration density are improved, but error rate during manufacturing and operation increases
Solution Approach 1:
The patent implements preliminary testing and repair actions during the manufacturing process itself. The test device detects defective memory cells and the repair device corrects them before the semiconductor chip is packaged and shipped, preventing defective cells from reaching the customer and reducing field failure rates.
Solution Approach 2:
The patent incorporates self-diagnosis and self-repair capabilities within the memory device. Through built-in test circuits and repair logic, the memory device can automatically identify defective cells and redirect access to those locations to redundant cells, enabling the system to correct its own manufacturing defects without external intervention.
2Reliability
If memory cells are tested and repaired after chip packaging, then field reliability is improved, but test and repair complexity increases
Solution Approach 1:
The patent combines the test device and repair device into an integrated system that can perform both functions. The test device identifies defective cells and automatically provides fail address information to the repair device, which then performs the repair operation. This merging reduces the need for separate, complex testing and repair equipment.
Solution Approach 2:
The patent introduces a fail address memory as an intermediary component that stores the addresses of defective memory cells. This intermediary allows the test device to communicate defect information to the repair device without requiring direct complex interaction between the two devices, simplifying the overall system architecture.
3Measurement precision
If fail address is temporarily stored and then transmitted to non-volatile storage array, then repair accuracy is improved, but storage and transmission time increases
Solution Approach 1:
The patent performs preliminary detection and recording of fail addresses during the testing phase. By identifying and storing defective cell addresses in the fail address memory before the repair operation begins, the system prepares the necessary information in advance, enabling faster execution of the repair process without compromising accuracy.
Data Source
AI summary
Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.