Semiconductor Memory Soft-Post-Package Repair Lock Mechanism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently performing soft-post-package repair operations, including the need for a reliable Undo command to cancel repairs and a Lock command to prevent execution of Undo operations, which are not adequately addressed in existing technologies.
Innovation Solution
The semiconductor memory device incorporates an anti-fuse cell array and a data converter, controlled by an anti-fuse controller, to manage fuse data and perform soft-post-package repairs and Undo operations, utilizing match signals and lock flags to enable or prohibit these commands, ensuring accurate address latching and redundancy selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If soft-post-package repair operation is implemented, then repair flexibility is improved, but command control complexity increases due to need for Undo and Lock commands
Solution Approach 1:
The Lock command is executed in advance before the Undo command to prevent unauthorized or unintended operations. This preliminary locking action establishes control state before the repair cancellation operation, ensuring system stability during the transition.
Solution Approach 2:
The system implements feedback mechanisms through status signals that indicate whether a memory bank is locked or unlocked, and whether repair operations have been successfully completed or canceled. This feedback allows the control logic to manage the complexity of multiple commands by providing clear state information.
2Ease of operation
If Undo command is added to cancel soft-post-package repair, then operational reversibility is improved, but reliability may deteriorate due to potential unintended changes
Solution Approach 1:
The Lock command serves as a preliminary protective action that prevents unintended operations on locked memory banks. By establishing this protective state before allowing Undo operations, the system prevents accidental data corruption while maintaining the ability to reverse legitimate repair operations.
Solution Approach 2:
The Lock command acts as an intermediary control mechanism between the Undo command and the actual memory bank state. It mediates the interaction by requiring explicit authorization (unlocking) before allowing state changes, thus preventing unintended changes while enabling operational reversibility.
3Reliability
If Lock command is implemented to prohibit Undo operation, then reliability is improved, but device complexity increases
Solution Approach 1:
The Lock command applies local control to specific memory banks rather than affecting the entire device. Each memory bank can be independently locked or unlocked, allowing selective protection only where needed. This localized approach reduces overall system complexity compared to a global locking mechanism.
Solution Approach 2:
The control mechanism is segmented into separate Lock and Unlock operations that can be independently managed. This segmentation allows the complexity to be divided into discrete, manageable functions that operate on individual memory banks, reducing the complexity burden on the overall control logic.
4Measurement precision
If address latching is performed during soft-post-package repair, then repair accuracy is improved, but operation time increases
Solution Approach 1:
The address latching is performed as a preliminary action during the repair operation setup phase, before the actual repair execution begins. By completing the address latching in advance, the system ensures accuracy is established early, and the subsequent repair operation can proceed more quickly without repeated latching operations.
Data Source
AI summary
Disclosed herein is an apparatus that includes a first address generator generating a first address in response to a clock signal; a second address generator generating a second address corresponding to the first address; a first detection circuit activating a first signal when the second address matches with a third address; a second detection circuit activating a second signal when the second address indicates a predetermined state; a first latch circuit latching the first address in response to the first signal; a second latch circuit latching the first address in response to the second signal; a third detection circuit activating a third signal when the first address matches with an address stored in the first latch circuit; a fourth detection circuit activating a fourth signal when the first address matches with an address stored in the second latch circuit; and a first selector selecting the third or fourth signal.